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| intel corporation order number: 245103-003 mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz available at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz supports the intel architecture with dynamic execution integrated primary 16-kbyte instruction cache and 16-kbyte write back data cache integrated second level cache (256-kbyte) micro-pga and bga packaging technologies supports thin form factor notebook designs exposed die enables more efficient heat dissipation fully compatible with previous intel microprocessors binary compatible with all applications support for mmx? technology power management features quick start and deep sleep modes provide extremely low power dissipation low-power gtl+ processor system bus interface integrated math co-processor integrated thermal diode the intel mobile pentium ii processor introduces a higher level of performance for todays mobile computing environment, including multimedia enhancements and improved internet and communications capabilities. it provides an improved performance 1 available for applications running on advanced operating systems such as windows* 98. on top of its built-in power management capabilities, the pentium ii processor takes advantage of software designed for intels mmx technology to unleash enhanced color, smoother graphics and other multimedia and communications enhancements. the mobile pentium ii processor may contain design defects or errors know as errata that may cause the product to deviate from published specifications. current characterized errata are available upon request. 1. refer to the mobile pentium ii processor performance brief .
mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz ii intel corporation information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of intel products. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a par ticular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving or life sustaining applications. intel retains the right to make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising fro m future changes to them. the mobile pentium? ii processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature, may be obtained by calling 1-800-548-4725 or by visiting intels website at http://www.intel.com copyright ? intel corporation, 1999. *third-party brands and names are the property of their respective owners . mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation iii contents page page 1. introduction .............................................. 1 1.1 overview.................................................... 2 1.2 terminology ............................................... 2 1.3 references ................................................ 2 2. mobile pentium ? ii processor features ...................................................... 4 2.1 feature differences between the mobile pentium ? ii processor at 400 mhz and mobile pentium ? ii processor at 366 mhz and below ........................................................ 4 2.2 power management ................................... 4 2.2.1 clock control architecture ................ 4 2.2.2 normal state .................................... 6 2.2.3 auto halt state ................................. 6 2.2.4 stop grant state......................... 6 2.2.5 quick start state ........................ 6 2.2.6 halt/grant snoop state............ 7 2.2.7 sleep state .................................... 8 2.2.8 deep sleep state ............................. 8 2.2.9 operating system implications of quick start and sleep states............ 8 2.3 low power gtl+ ....................................... 8 2.3.1 gtl+ signals.................................... 9 2.4 mobile pentium ? ii processor cpuid......... 9 3. electrical specifications .................. 11 3.1 processor system signals ....................... 11 3.1.1 power sequencing requirements... 12 3.1.2 test access port (tap) connection 13 3.1.3 catastrophic thermal protection .... 13 3.1.4 unused signals .............................. 13 3.1.5 signal state in low power states ... 13 3.2 power supply requirements .................... 14 3.2.1 decoupling recommendations ....... 14 3.2.2 voltage planes ............................... 14 3.3 system bus clock and processor clocking15 3.4 maximum ratings .................................... 16 3.5 dc specifications..................................... 18 3.6 ac specifications ..................................... 23 3.6.1 system bus, clock, apic, tap, cmos and open-drain ac specifications ................................. 23 4. system signal simulations ................. 37 4.1 system bus clock (bclk) signal quality specifications........................................... 37 4.2 low power gtl+ signal quality specifications........................................... 38 4.3 non-low power gtl+ signal quality specifications........................................... 41 4.3.1 overshoot and undershoot guidelines42 4.3.1 ringback specification.................... 43 4.3.2 settling limit guideline ................... 43 5. mechanical specifications ................. 44 5.1 dimensions of the micro-pga package ... 44 5.2 dimensions of the bga package ............. 46 5.3 signal listings.......................................... 49 6. thermal specifications........................ 62 6.1 thermal diode.......................................... 63 6.2 case temperature ................................... 64 7. processor initialization and configuration.......................................... 65 7.1 description ............................................... 65 7.1.1 quick start enable.......................... 65 7.1.2 system bus frequency................... 65 7.1.3 apic disable .................................. 65 7.2 clock frequencies and ratios.................. 65 8. processor interface............................ 66 8.1 alphabetical signal reference ................. 66 8.2 signal summaries .................................... 72 mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz iv intel corporation list of figures page figure 1.1 signal groups of a mobile pentium ? ii processor-based system .................... 1 figure 2.1 clock control states............................. 5 figure 3.1 ramp rate requirement ..................... 13 figure 3.2 pll lc filter ...................................... 14 figure 3.3 generic clock waveform.................... 30 figure 3.4 valid delay timings............................ 31 figure 3.5 setup and hold timings ..................... 31 figure 3.6 reset and configuration timings........ 32 figure 3.7 power-on reset timings.................... 33 figure 3.8 test timings (boundary scan) ........... 34 figure 3.9 test reset timings............................. 34 figure 3.10 quick start/deep sleep timing......... 35 figure 3.11 stop grant/sleep/deep sleep timing36 figure 4.1 bclk generic clock waveform ......... 38 figure 4.2 gtl+ receiver ringback tolerance .... 39 figure 4.3 maximum acceptable gtl+ overshoot/undershoot waveform for the mobile pentium? ii processor at 400 mhz ............................................ 41 figure 4.4 non-gtl+ signal ringback and settling limit................................................... 42 figure 5.1 micro-pga package-top and side view................................................... 45 figure 5.2 micro-pga package - bottom view .... 46 figure 5.3 surface-mount bga package - top and side view........................................... 48 figure 5.4 surface-mount bga package - bottom view................................................... 49 figure 5.5 pin/ball map - top view ..................... 50 figure 6.1 technique for measuring case temperature ...................................... 64 figure 8.1 pwrgood relationship at power-on70 mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation v list of tables page page table 2.1 vtol, cmos and open drain signal characteristics..................................... 4 table 2.2 clock state characteristics.................... 7 table 2.3 mobile pentium ii processor cpuid .... 9 table 2.4 mobile pentium ii processor cpuid cache and tlb descriptors ................. 9 table 3.1 system signal groups ......................... 11 table 3.2 recommended resistors for open drain signals............................................... 12 table 3.3 lc filter specifications ........................ 15 table 3.4 core frequency to system bus ratio configuration ..................................... 15 table 3.5 absolute maximum ratings for mobile pentium ii processor at 400 mhz .... 16 table 3.6 absolute maximum ratings for mobile pentium ii processor at 366 mhz and below................................................. 17 table 3.7 power specifications for mobile pentium? ii processor at 400 mhz.... 18 table 3.8 power specifications for mobile pentium? ii processor at 366 mhz and below................................................. 19 table 3.9 power specifications for low voltage pentium? ii processor....................... 20 table 3.10 low power gtl+ signal group dc specifications .................................... 21 table 3.11. low power gtl+ bus dc specifications .................................... 21 table 3.12 clock, apic, tap, cmos and open- drain signal group dc specifications for the mobile pentium? ii processor at 400 mhz ............................................ 22 table 3.13 clock, apic, tap, cmos and open- drain signal group dc specifications for the mobile pentium? ii processor at 366 mhz and below........................... 23 table 3.14 system bus clock ac specifications. 24 table 3.15 valid mobile pentium ii processor frequencies....................................... 25 table 3.16 low power gtl+ signal groups ac specifications .................................... 25 table 3.17 cmos and open-drain signal groups ac specifications .............................. 26 table 3.18 reset configuration ac specifications27 table 3.19 tap signal ac specifications ............ 28 table 3.20 quick start/deep sleep ac specifications..................................... 29 table 3.21 stop grant/sleep/deep sleep ac specifications..................................... 29 table 4.1 bclk signal quality specifications...... 37 table 4.2 low power gtl+ signal group ringback specification for the mobile pentium? ii processor .......................................... 39 table 4.3. gtl+ signal group overshoot/undershoot tolerance at the processor core for the mobile pentium? ii processor at 400 mhz ............................................ 40 table 4.4 signal ringback specifications for non- gtl+ signals for the mobile pentium? ii processor at 400 mhz..................... 43 table 4.5 signal ringback specifications for non- gtl+ signals for the mobile pentium? ii processor at 366 mhz and below ... 43 table 5.1 micro-pga package mechanical specifications..................................... 44 table 5.2 surface-mount bga package specifications..................................... 47 table 5.3 signal listing in order by pin/ball number.............................................. 51 table 5.4 signal listing in order by signal name 57 table 5.5 voltage and no-connect ball/pin locations ........................................... 61 table 6.1 mobile pentium ii processor (0.18 m) power specifications.......................... 62 table 6.2 thermal diode interface....................... 63 table 6.3. thermal diode specifications ............. 63 table 8.1 input signals ........................................ 73 table 8.2 output signals ..................................... 74 table 8.3 input/output signals (single driver) ..... 74 table 8.4 input/output signals (multiple driver)... 75 mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 1 1. introduction the mobile pentium? ii processor is now offered at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz, with a system bus speed of 66 mhz. the mobile pentium? ii processor at 400 mhz in micro-pga and bga packages are the first mobile processors manufactured in 0.18 m technology. processors at frequencies 366 mhz and below are manufactured in 0.25 m processing technology. the mobile pentium? ii processor consists of a processor core with an integrated l2 cache and a 64-bit high performance system bus. the integrated l2 cache is designed to help improve performance; it complements the system bus by providing critical data faster and reducing total system power consumption. the mobile pentium? ii processors 64-bit wide low power gunning transceiver logic (gtl+) system bus is compatible with the 440bx agpset and provides a glue-less, point-to-point interface for an i/o bridge/memory controller. figure 1.1 shows the various parts of a mobile pentium ii processor-based system and how the mobile pentium ii processor connects to them. mobile pentium? ii processor 443bx north bridge piix4e/m south bridge pci isa/eio tap cmos/ open drain dram system bus thermal sensor smbus system controller v0000-05 or figure 1.1 signal groups of a mobile pentium ? ii processor-based system mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 2 intel corporation 1.1 overview ? performance improved over existing mobile processors ? supports the intel architecture with dynamic execution ? supports the intel architecture mmx technology ? integrated intel floating-point unit compatible with the ieee 754 standard ? integrated primary (l1) instruction and data caches ? 4-way set associative, 32-byte line size, 1 line per sector ? 16-kbyte instruction cache and 16-kbyte writeback data cache ? cacheable range programmable by processor programmable registers ? integrated second level (l2) cache ? 4-way set associative, 32-byte line size, 1 line per sector ? operates at full core speed ? 256-kbyte, ecc protected cache data array ? 4 gbyte cacheable range ? low power gtl+ system bus interface ? 64-bit data bus, 66-mhz operation ? uniprocessor, two loads only (processor and i/o bridge/memory controller) ? short trace length and low capacitance allows for single ended termination ? voltage reduction technology ? advanced processor clock control ? quick start for low power, low exit latency clock throttling ? deep sleep mode for extremely low power dissipation ? thermal diode for measuring processor temperature 1.2 terminology in this document a # symbol following a signal name indicates that the signal is active low. this means that when the signal is asserted (based on the name of the signal) it is in an electrical low state. otherwise, signals are driven in an electrical high state when they are asserted. in state machine diagrams, a signal name in a condition indicates the condition of that signal being asserted. if the signal name is preceded by a ! symbol, then it indicates the condition of that signal not being asserted. for example, the condition !stpclk# and hs is equivalent to the active low signal stpclk# is unasserted (i.e., it is at 1.5v for the 400 mhz, and 2.5v for the 366 mhz and below) and the hs condition is true. the symbols l and h refer respectively to electrical low and electrical high signal levels. the symbols 0 and 1 refer respectively to logical low and logical high signal levels. for example, bd[3:0] = 1010 = hlhl refers to a hexadecimal a, and d[3:0]# = 1010 = lhlh also refers to a hexadecimal a. 1.3 references pentium ? ii processor at 233 mhz, 266 mhz, 300 mhz and 333 mhz (order number 243335) pentium ? ii processor developers manual (order number 243502) ckdm66-m clock driver specification (contact your intel field sales representative) ck97 clock driver specification (contact your intel field sales representative) intel architecture software developers manual (order number 243193) volume i: basic architecture (order number 243190) volume ii: instruction set reference (order number 243191) volume iii: system programming guide (order number 243192) mobile pentium ii processor (0.18 m)i/o buffer models, ibis format (available in electronic form; contact your intel field sales representative) mobile pentium ? ii processor system bus layout guideline (order number 243672-001) mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 3 mobile pentium ? ii processor mechanical and thermal design guide (order number 243671-001) mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 4 intel corporation 2. mobile pentium ? ii processor features 2.1 feature differences between the mobile pentium ? ii processor at 400 mhz and mobile pentium ? ii processor at 366 mhz and below power specifications cpuid cmos/open drain signal voltage tolerance pull-up/pull-down recommendation for almost all signals cmos signal dc specifications cmos signal ac specifications vtol pin impedance core voltages, v cc and v ccp table 2.1 vtol, cmos and open drain signal characteristics mobile pentium? ii processor vtol pin cmos/open drain signal voltage tolerance (v cmos ) cmos/open drain signal trip voltage (v trip ) 400 mhz short to vss 1.5v 0.75v 366 mhz and below high impedance 2.5v 1.25v 2.2 power management 2.2.1 clock control architecture the mobile pentium ii processor clock control architecture (figure 2.1) has been optimized for leading edge deep green desktop and mobile computer designs. the auto halt state provides a low power clock state that can be controlled through the software execution of the hlt instruction. the quick start state provides a very low power, low exit latency clock state that can be used for hardware controlled idle computer states. the deep sleep state provides an extremely low power state that can be used for power-on suspend computer states, which is an alternative to shutting off the processors power. compared to the pentium processor exit latency of 1 msec, the exit latency of the deep sleep state has been reduced to 30 sec in the mobile pentium ii processor. the stop grant and sleep states shown in figure 2.1 are intended for use in deep green desktop and server systems not in mobile systems. performing state transitions not shown in figure 2.1 is neither recommended nor supported. the clock control architecture consists of seven different clock states: normal, auto halt, stop grant, quick start, halt/grant snoop, sleep and deep sleep states. the stop grant and quick start clock states are mutually exclusive, i.e., a strapping option on signal a15# chooses which state is entered when the stpclk# signal is asserted. strapping the a15# signal to ground at reset enables the quick start state; otherwise, asserting the stpclk# signal puts the processor into the stop grant state. the stop grant state has a higher power level than the quick start state and is designed for smp platforms. the quick start state has a much lower power level, but it can only be used in uniprocessor platforms. table 2.2 provides clock state characteristics (power numbers based on estimates for a mobile pentium ii processor at 400 mhz and 366 mhz), which are described in detail in the following sections. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 5 halt/grant snoop normal hs=false stop grant auto halt hs=true quick start sleep deep sleep (!stpclk# and !hs) or stop break stpclk# and !qse and sga snoop occurs snoop serviced stpclk# and qse and sga (!stpclk# and !hs) or reset# snoop serviced snoop occurs !stpclk# and hs stpclk# and !qse and sga hlt and halt bus cycle halt break snoop serviced snoop occurs stpclk# and qse and sga !stpclk# and hs !slp# or reset# slp# bclk stopped bclk on and !qse bclk stopped bclk on and qse v0001-00 notes: halt break - a20m#, binit#, flush#, init#, intr, nmi, preq#, reset#, smi# hlt - hlt instruction executed hs - processor halt state qse - quick start state enabled sga - stop grant acknowledge bus cycle issued stop break - binit#, flush#, reset# figure 2.1 clock control states mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 6 intel corporation 2.2.2 normal state the normal state of the processor is the normal operating mode where the processors internal clock is running and the processor is actively executing instructions. 2.2.3 auto halt state this is a low power mode entered by the processor through the execution of the hlt instruction. the power level of this mode is similar to the stop grant state. a transition to the normal state is made by a halt break event (one of the following signals going active: nmi, intr, binit#, init#, reset#, flush# or smi#). asserting the stpclk# signal while in the auto halt state will cause the processor to transition to the stop grant or quick start state, where a stop grant acknowledge bus cycle will be issued. deasserting stpclk# will cause the processor to return to the auto halt state without issuing a new halt bus cycle. the smi# interrupt is recognized in the auto halt state. the return from the system management interrupt (smi) handler can be to either the normal state or the auto halt state. see the intel ? architecture software developers manual, volume iii: system programmers guide for more information. no halt bus cycle is issued when returning to the auto halt state from system management mode (smm). the flush# signal is serviced in the auto halt state. after the on-chip and off-chip caches have been flushed, the processor will return to the auto halt state without issuing a halt bus cycle. transitions in the a20m# and preq# signals are recognized while in the auto halt state. 2.2.4 stop grant state the processor enters this mode with the assertion of the stpclk# signal when it is configured for stop grant state (via the a15# strapping option). the processor is still able to respond to snoop requests and latch interrupts. latched interrupts will be serviced when the processor returns to the normal state. only one occurrence of each interrupt event will be latched. a transition back to the normal state can be made by the de-assertion of the stpclk# signal, or the occurrence of a stop break event (a binit#, flush# or reset# assertion). the processor will return to the stop grant state after the completion of a binit# bus initialization unless stpclk# has been de-asserted. reset# assertion will cause the processor to immediately initialize itself, but the processor will stay in the stop grant state after initialization until stpclk# is deasserted. if the flush# signal is asserted, the processor will flush the on-chip caches and return to the stop grant state. a transition to the sleep state can be made by the assertion of the slp# signal. while in the stop grant state, assertions of smi#, init#, intr and nmi will be latched by the processor. these latched events will not be serviced until the processor returns to the normal state. only one of each event will be recognized upon return to the normal state. 2.2.5 quick start state this is a mode entered by the processor with the assertion of the stpclk# signal when it is configured for the quick start state (via the a15# strapping option). in the quick start state the processor is only capable of acting on snoop transactions generated by the system bus priority device. because of its snooping behavior, quick start can only be used in a uniprocessor (up) configuration. a transition to the deep sleep state can be made by stopping the clock input to the processor. a transition back to the normal state (from the quick start state) is made only if the stpclk# signal is deasserted. while in this state the processor is limited in its ability to respond to input. it is incapable of latching any interrupts, servicing snoop transactions from symmetric bus masters or responding to flush# or mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 7 binit# assertions. while the processor is in the quick start state, it will not respond properly to any input signal other than stpclk#, reset# or bpri#. if any other input signal changes, then the behavior of the processor will be unpredictable. no serial interrupt messages may begin or be in progress while the processor is in the quick start state. reset# assertion will cause the processor to immediately initialize itself, but the processor will stay in the quick start state after initialization until stpclk# is deasserted. table 2.2 clock state characteristics clock state exit latency power snooping? system uses normal n/a varies yes normal program execution auto halt approximately 10 bus clocks 1.25 w yes s/w controlled entry idle mode stop grant approximately 10 bus clocks 1.25 w yes h/w controlled entry/exit mobile throttling quick start through snoop, to halt/grant snoop state: immediate through stpclk#, to normal state: 8 bus clocks 0.5 w yes h/w controlled entry/exit mobile throttling halt/grant snoop a few bus clocks after the end of snoop activity. not specified yes supports snooping in the low power states sleep to stop grant state 10 bus clocks 0.5 w no h/w controlled entry/exit desktop idle mode support deep sleep 30 sec 150 mw no h/w controlled entry/exit powered-on suspend support note: not 100% tested. specified at 50c by design/characterization. 2.2.6 halt/grant snoop state the processor will respond to snoop transactions on the system bus while in the auto halt, stop grant or quick start state. when a snoop transaction is presented on the system bus the processor will enter the halt/grant snoop state. the processor will remain in this state until the snoop has been serviced and the system bus is quiet. after the snoop has been serviced, the processor will return to its previous state. if the halt/grant snoop state is entered from the quick start state, then the input signal restrictions of the quick start state still apply in the halt/grant snoop state, except for those signal transitions that are required to perform the snoop. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 8 intel corporation 2.2.7 sleep state the sleep state is a very low power state in which the processor maintains its context and the phase- locked loop (pll) maintains phase lock. the sleep state can only be entered from the stop grant state. after entering the stop grant state, the slp# signal can be asserted, causing the processor to enter the sleep state. the slp# signal is not recognized in the normal or auto halt states. the processor can be reset by the reset# signal while in the sleep state. if reset# is driven active while the processor is in the sleep state then slp# and stpclk# must immediately be driven inactive to ensure that the processor correctly initializes itself. input signals (other than reset#) may not change while the processor is in the sleep state or transitioning into or out of the sleep state. input signal changes at these times will cause unpredictable behavior. thus, the processor is incapable of snooping or latching any events in the sleep state. while in the sleep state, the processor can enter its lowest power state, the deep sleep state. removing the processors input clock puts the processor in the deep sleep state. picclk may be removed in the sleep state. 2.2.8 deep sleep state the deep sleep state is the lowest power mode the processor can enter while maintaining its context. the deep sleep state is entered by stopping the bclk input to the processor, while it is in the sleep or quick start state. for proper operation, the bclk input should be stopped in the low state. the processor will return to the sleep or quick start state from the deep sleep state when the bclk input is restarted. due to the pll lock latency, there is a 30 sec delay after the clocks have started before this state transition happens. picclk may be removed in the deep sleep state. picclk should be designed to turn on when bclk turns on when transitioning out of the deep sleep state. the input signal restrictions for the deep sleep state are the same as for the sleep state, except that reset# assertion will result in unpredictable behavior. 2.2.9 operating system implications of quick start and sleep states there are a number of architectural features of the mobile pentium ? ii processor that are not available when the quick start state is enabled or do not function in the quick start or sleep state as they do in the stop grant state. these features are part of the time-stamp counter and performance monitor counters. the time-stamp counter and the performance monitor counters are not guaranteed to count in the quick start or sleep states. 2.3 low power gtl+ the mobile pentium ? ii processor system bus signals use a variation of the low voltage swing gtl signaling technology. the mobile pentium ii processor system bus specification is similar to the pentium ii processor system bus specification, which is a version of gtl with enhanced noise margins and less ringing. the mobile pentium ii processor system bus specification reduces system cost and power consumption by raising the termination voltage and termination resistance and changing the termination from dual ended to single ended. because the specification is different from the standard gtl specification and from the pentium ii processor gtl+ specification, it is referred to as low power gtl+. the pentium ii processor gtl+ system bus depends on incident wave switching and uses flight time for timing calculations of the gtl+ signals. the low power gtl+ system bus is short and lightly loaded. with low power gtl+ signals, timing calculations are based on capacitive derating. analog signal simulation of the system bus including trace lengths is highly recommended to ensure that there are no significant transmission line effects. contact your field sales representative to receive the ibis models for the mobile pentium ii processor. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 9 the gtl+ system bus of the pentium ii processor was designed to support high-speed data transfers with multiple loads on a long bus that behaves like a transmission line. however, in a mobile system, the system bus only has two loads (the processor and the chipset) and the bus traces are short enough that transmission line effects are not significant. it is possible to change the layout and termination of the system bus to take advantage of the mobile environment using the same gtl+ i/o buffers. the benefit is that it reduces the number of terminating resistors in half and substantially reduces the ac and dc power dissipation of the system bus. low power gtl+ uses gtl+ i/o buffers but only two loads are allowed. the trace length is limited and the bus is terminated at one end only. since the system bus is small and lightly loaded, it behaves like a capacitor, and the gtl+ i/o buffers behave like high-speed open-drain buffers. with a 66-mhz bus frequency, the pull-up would be 120 . if 100 termination resistors are used rather than 120 , then 20% more power will be dissipated in the termination resistors. 120 termination is recommended to conserve power. refer to the mobile pentium ? ii processor system bus layout guideline (order number 243672-001) for details on laying out the low power gtl+ system bus. 2.3.1 gtl+ signals two signals of the system bus can potentially not meet the low power gtl+ layout requirements: prdy# and reset#. these two signals connect to the debug port and might not meet the maximum length requirements. if prdy# or reset# do not meet the layout requirements for low power gtl+, then they must be terminated using dual-ended termination at 120 . higher resistor values can be used if simulations show that the signal quality specifications in section 4 are met. 2.4 mobile pentium ? ii processor cpuid the mobile pentium ii processor has the same cpuid family and model number as some celeron? processors. the mobile pentium ii processor can be distinguished from these celeron processors by looking at the stepping number and the cpuid cache descriptor information. a mobile pentium ii processor has a stepping number in the range of 0ah to 0fh (0ah to 0ch for the 400 mhz, 0dh to 0fh for the 366 mhz and below) and an l2 cache descriptor of 042h (256-kbyte l2 cache). if the stepping number is less than 0ah or the l2 cache descriptor is not 042h then the processor is a celeron processor. the l2 cache must be properly initialized for the l2 cache descriptor information to be correct. after a power-on reset, or when the cpuid instruction is executed, the eax register contains the values shown in table 2.3. after the l2 cache is initialized, the cpuid cache/tlb descriptors will be the values shown in table 2.4. table 2.3 mobile pentium ii processor cpuid reserved [31:14] type [13:12] family [11:8] model [7:4] stepping [3:0] 0dhC 0fh (400 mhz) x066 0ah C 0ch (366 mhz and below) table 2.4 mobile pentium ii processor cpuid cache and tlb descriptors cache and tlb descriptors 01h, 02h, 03h, 04h, 08h, 0ch, 42h mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 10 intel corporation mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 11 3. electrical specifications 3.1 processor system signals table 3.1 lists the processor system signals by type. all low power gtl+ signals are synchronous with the bclk signal. all tap signals are synchronous with the tck signal except trst#. all cmos input signals can be applied asynchronously. table 3.1 system signal groups group name signals low power gtl+ input bpri#, defer#, reset#, rs[2:0]#, rsp#, trdy# low power gtl+ output prdy# low power gtl+ i/o a[35:3]#, ads#, aerr# 5 , ap[1:0]#, berr#, binit#, bnr#, bp[3:2]#, bpm[1:0]#, breq0#, d[63:0]#, dbsy#, dep[7:0]#, drdy#, hit#, hitm#, lock#, req[4:0]#, rp# cmos input 1, 2 a20m#, bsel, flush#, ignne#, init#, intr, nmi, preq#, pwrgood, slp#, smi#, stpclk# open drain output 2 ferr#, ierr#, vtol clock 3 bclk apic clock 2 picclk apic i/o 2 picd[1:0] thermal diode thermda, thermdc tap input 2 tck, tdi, tms, trst# tap output 2 tdo power/other 4 edgectrln, nc, pll1, pll2, testhi, testhi2, testhi3, testlo, v cc , v ccp , v ref , v ss notes: 1. see section 8 for information on the pwrgood signal. 2. except for the 1.6v tolerant vtol, these signals are tolerant to 1.5v for the 400 mhz, and 2.5v tolerant for the 366 mhz and below. see table 3.2 for the recommended pull-up resistor. 3. bclk is a 2.5v tolerant signal. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 12 intel corporation 4. v cc is the power supply for the core logic. pll1 and pll2 are the power supply for the pll analog section. v ccp is the power supply for the cmos voltage references. v ref is the voltage reference for the low power gtl+ input buffers. v ss is system ground. 5. the aerr# processor bus pin is removed as a processor feature for the 400 mhz. the pin must still be terminated to v cc through a 120 pull-up resistor. but the processor must not be configured to drive or observe the pin. the cmos and tap inputs can be driven from ground to v cmos . the tap outputs are open drain and should be pulled up to v cmos using resistors with the values shown in table 3.2. if open drain drivers are used for input signals, then they should also be pulled up to v cmos using resistors with the values shown in table 3.2. table 3.2 recommended resistors for open drain signals recommended resistor value ( ) open drain signal 1 150 pull-up tdi, tdo, testhi3 2 680 pull-up stpclk# 1k pull-up init#, tck, testhi, testhi2, testhi3 2 , tms 680 - 1k pull-down trst# 1.5k pull-up (400 mhz) 4.7k pull-up (366 mhz and below) a20m#, ferr#, flush#, ierr#, ignne#, intr, nmi, preq#, pwrgood, slp#, smi#, vtol note: 1. refer to section 3.1.4 for the required pull-up or pull-down resistors for signals that are not being used. 2. the testhi3 signal must be pulled up to v cc using a 150 resistor on 400 mhz processors. on 366 mhz and below the resistor may be between 150 and 1k . 3.1.1 power sequencing requirements the mobile pentium ? ii processor has no power sequencing requirements. it is recommended that all of the processor power planes rise to their specified values within one second of each other. the v cc power plane must not rise too fast. at least 200 sec (t r ) must pass from the time that v cc is at 10% of its nominal value until the time that v cc is at 90% of its nominal value (see figure 3.1). mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 13 90% v cc (nominal) volts t r v cc 10% v cc (nominal) time figure 3.1 ramp rate requirement 3.1.2 test access port (tap) connection the tap interface is an implementation of the ieee 1149.1 (jtag) standard. due to the voltage levels supported by the tap interface, it is recommended that the mobile pentium ii processor and the other 1.5v/2.5v jtag specification compliant devices be last in the jtag chain after any devices with 3.3v or 5v jtag interfaces within the system. a translation buffer should be used to reduce the tdo output voltage of the last 3.3/5v device down to the v cmos range that the mobile pentium ii processor can tolerate. multiple copies of tck, tms, and trst# must be provided, one for each voltage level. a debug port and connector may be placed at the start and end of the jtag chain containing the processor, with tdi to the first component coming from the debug port and tdo from the last component going to the debug port. there are no requirements for placement of the mobile pentium ii processor in the jtag chain, except for those that are dictated by voltage requirements of the tap signals. 3.1.3 catastrophic thermal protection the mobile pentium ii processor does not support catastrophic thermal protection or the thermtrip# signal. an external thermal sensor should use the thermal diode to protect the processor and the system against excessive temperatures. 3.1.4 unused signals all signals named nc must be unconnected. all signals named testlo must be pulled down to v ss , or tied directly to v ss . all signals named testhi or testhi3 must be pulled up to v cc with a resistor. all signals named testhi2 must be pulled up to v ccp with a resistor. each testhi and testhi2 signal must have an individual, 1k pull- up resistor. the testhi3 signals can share a single pull-up of 150 for the 400 mhz processor and 150 to 1k for 366 mhz and below. unused low power gtl+ inputs, outputs and bi- directional signals should be individually connected to v cc with 120 pull-up resistors. unused cmos active low inputs should be connected to v cmos . unused active high inputs should be connected to v ss . unused open-drain outputs should be unconnected. if the processor is configured to enter the quick start state rather than the stop grant state, then the slp# signal should be connected to v cmos . when tying any signal to power or ground, a resistor will allow for system testability. for unused signals, it is suggested that 1k resistors be used for pull-ups and for pull-downs. picclk and picd[1:0] must be tied to v ss with a 1k resistor. bsel must be connected to v ss. 3.1.5 signal state in low power states 3.1.5.1 system bus signals all of the system bus signals have low power gtl+ input, output or input/output drivers. except when servicing snoops, the system bus signals are tri- stated and pulled up by the termination resistors. snoops are not permitted in the sleep and deep sleep states. 3.1.5.2 cmos and open-drain signals the cmos input signals are allowed to be in either the logic high or low state when the processor is in a mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 14 intel corporation low power state. in the auto halt and stop grant states these signals are allowed to toggle. these input buffers have no internal pull-up or pull-down resistors and system logic can use cmos or open- drain drivers to drive them. the open-drain output signals have open drain drivers and external pull-up resistors are required. one of the two output signals (ierr#) is a catastrophic error indicator and is tri-stated (and pulled-up) when the processor is functioning normally. the ferr# output can be either tri-stated or driven to v ss when the processor is in a low power state, depending on the condition of the floating point unit. since this signal is a dc current path when it is driven to v ss , it is recommended that the software clears or masks any floating point error condition before putting the processor into the deep sleep state. 3.1.5.3 other signals the system bus clock (bclk) must be driven in all of the low power states except the deep sleep state. 3.2 power supply requirements 3.2.1 decoupling recommendations the amount of bulk decoupling required to meet the processor voltage tolerance requirements is a strong function of the power supply design. contact your intel field sales representative for tools to help determine how much decoupling is required. the processor core power plane (v cc ) should have at least twenty-six 0.1 f high frequency decoupling capacitors. the cmos voltage reference power plane (v ccp ) requires 50 to 100 f of bulk decoupling and at least eight 0.1 f high frequency decoupling capacitors. for the low power gtl+ pull-up resistors, one 0.1 f high frequency decoupling capacitor is recommended per resistor pack. there should be no more than eight pull-up resistors per resistor pack. the low power gtl+ voltage reference power plane (v ref ) should have at least three 0.1 f high frequency decoupling capacitors. 3.2.2 voltage planes all v cc and v ss balls/pins must be connected to the appropriate voltage plane. all v ccp and v ref balls/pins must be connected to the appropriate traces on the system electronics. in addition to the main v cc , v ccp and v ss power supply signals, pll1 and pll2 provide isolated power to the pll section. pll1 and pll2 should be connected according to figure 3.2. do not connect pll2 directly to v ss . a separate power supply should be used to generate v ccp to isolate the pll from processor core noise. table 3.3 contains the requirements for c1 and l1. pll1 pll2 v ccp v0027-00 l1 c1 figure 3.2 pll lc filter mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 15 table 3.3 lc filter specifications symbol parameter min max unit notes c1 lc filter capacitance 47 f 30% tolerance, 1 max series resistance, ~2nh series inductance l1 lc filter inductance 20 47 h low-q type choke, 30% tolerance, 1.5 max series resistance, 50ma current, self-resonant frequency >10 mhz 3.3 system bus clock and processor clocking the 2.5v bclk clock input directly controls the operating speed of the system bus interface. all system bus timing parameters are specified with respect to the rising edge of the bclk input. the mobile pentium ii processor core frequency is a multiple of the bclk frequency. the mobile pentium? ii processor (0.18 m) at 400 mhz is implemented with the bus fraction locking scheme, which allows the processor to operate at the marked core frequency only. the bus ratio configuration signals are not effective. however, if desired, the signals can be set accordingly to table 3.4. table 3.4 core frequency to system bus ratio configuration processor core frequency to system bus frequency ratio nmi intr ignne# a20m# powerup configuration [25:22] 4/1 (266 mhz) l l l h 0010 9/2 (300 mhz) l h l h 0110 5/1 (333 mhz) l l h h 0000 11/2 (366 mhz) l h h h 0100 6/1 (400 mhz) h l l l 1011 the mobile pentium ii processors at 366 mhz and below frequencies are implemented with a bus fraction limiting scheme . a multiplexer is required between the system electronics and the processor to drive the bus ratio configuration signals during reset. figure 3.6 and table 3.18 describe the timing requirements for this operation. the 443bx creset# signal has suitable timing to control the multiplexer. after reset# and pwrgood are asserted, the multiplexer logic must guarantee that the bus ratio configuration signals encode one of the bus ratios in table 3.4 and that the bus ratio mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 16 intel corporation corresponds to a core frequency at or below the marked core frequency for the processor. the selected bus ratio is visible to software in the power- on configuration register, see section 7.2 for details. multiplying the bus clock frequency is necessary to increase performance while allowing for easier distribution of signals within the system. clock multiplication within the processor is provided by the internal phase lock loop (pll), which requires a constant frequency bclk input. during reset, or on exit from the deep sleep state, the pll requires some amount of time to acquire the phase of bclk. this time is called the pll lock latency, which is specified in section 3.6, ac timing parameters t18 and t47. except for the 400 mhz processor, the system bus frequency ratio can be changed when reset# is active, assuming that all reset specification are met. the bclk frequency should not be changed during deep sleep state (see section 2.2.8). 3.4 maximum ratings table 3.5 and table 3.6 contains the mobile pentium ii processor stress ratings. functional operation at the absolute maximum and minimum is neither implied nor guaranteed. the processor should not receive a clock while subjected to these conditions. functional operating conditions are provided in the ac and dc tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields. table 3.5 absolute maximum ratings for mobile pentium ii processor at 400 mhz symbol parameter min max unit notes t storage storage temperature C40 85 c note1 v cc (abs) supply voltage with respect to v ss C0.5 2.0 v v ccp cmos reference voltage with respect to v ss C0.3 2.0 v v in gtl+ buffer dc input voltage with respect to v ss C0.3 v cc + 0.5 v note 2 v in15 1.5v buffer dc input voltage with respect to v ss C0.3 2.0 v note 3 v blck blck buffer dc input voltage with respect to v ss C0.3 3.3 v notes: 1. the shipping container is only rated for 65c. 2. parameter applies to the low power gtl+ signal groups only. 3. parameter applies to cmos, open-drain, apic and tap bus signal groups only. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 17 table 3.6 absolute maximum ratings for mobile pentium ii processor at 366 mhz and below symbol parameter min max unit notes t storage storage temperature C40 85 c note1 v cc (abs) supply voltage with respect to v ss C0.5 3.0 v v ccp cmos reference voltage with respect to v ss C0.3 3.0 v v in gtl+ buffer dc input voltage with respect to v ss C0.3 v cc + 0.7 v note 2 v blck 2.5v buffer dc input voltage with respect to v ss C0.3 3.3 v note 3 notes: 1. the shipping container is only rated for 65c. 2. parameter applies to the low power gtl+ signal groups only. 3. parameter applies to cmos, open-drain, apic and tap bus signal groups only. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 18 intel corporation 3.5 dc specifications table 3.7 through table 3.12 list the dc specifications for the mobile pentium ii processor . specifications are valid only while meeting specifications for case temperature, clock frequency and input voltages. care should be taken to read all notes associated with each parameter. table 3.7 power specifications for mobile pentium? ii processor at 400 mhz t case = 0 to t case,max ; v cc = 1.5v 115mv; v ccp = 1.5v 90mv symbol parameter min typ max unit notes v cc v cc for core logic 1.385 1.500 1.615 v 115 mv v ccp v cc for cmos voltage references 1.410 1.500 1.590 v 90 mv i cc i cc for v cc at core @ 400 mhz frequency 7.10 a note 3 i ccp current for v ccp 100 ma notes 1, 2, 3 i cc,sg processor stop grant and auto halt current 1.29 a note 3 i cc,qs processor quick start and sleep current 994 ma note 3 i cc,dslp processor deep sleep leakage current 700 ma note 3 di cc /dt v cc power supply current slew rate 20 a/ s notes 4, 5 notes: 1. i ccp is the current supply for the cmos voltage references. 2. not 100% tested. specified by design/characterization. 3. i ccx,max specifications are specified at v cc,max , v ccp,max and 100c and under maximum signal loading conditions. 4. based on simulations and averaged over the duration of any change in current. use to compute the maximum inductance and reaction time of the voltage regulator. this parameter is not tested. 5. maximum values specified by design/characterization at nominal v cc and v ccp . mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 19 table 3.8 power specifications for mobile pentium? ii processor at 366 mhz and below t case = 0 to t case,max ; v cc = 1.6v 135mv; v ccp = 1.8v 90mv symbol parameter min typ max unit notes v cc v cc of core logic for regular voltage processors 1.465 1.600 1.735 v 135 mv v cc,lp v cc when i cc < 300 ma 1.465 1.600 1.805 v +205/-135 mv 1 v ccp v cc for cmos voltage references 1.710 1.800 1.890 v 1.8v 90 mv i cc i cc for v cc at core @ 366 mhz frequency @ 333 mhz @ 300pe mhz @ 266pe mhz 8.87 7.95 7.49 6.63 a a a a note 4 i ccp current for v ccp 75 ma notes 2, 3, 4 i cc,sg processor stop grant and auto halt current 1190 ma note 4 i cc,qs processor quick start and sleep current 880 ma note 4 i cc,dslp processor deep sleep leakage current 650 ma note 4 di cc /dt v cc power supply current slew rate 20 a/ s notes 5, 6 notes: 1. a higher vcc,max is allowed when the processor is in a low power state to enable high efficiency, low current modes in the power regulator. 2. i ccp is the current supply for the cmos voltage references. 3. not 100% tested. specified by design/characterization. 4. i ccx,max specifications are specified at v cc,max , v ccp,max and 100c and under maximum signal loading conditions. 5. based on simulations and averaged over the duration of any change in current. use to compute the maximum inductance and reaction time of the voltage regulator. this parameter is not tested. 6. maximum values specified by design/characterization at nominal v cc and v ccp . mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 20 intel corporation table 3.9 power specifications for low voltage pentium? ii processor t case = 0 to t case,max ; v cc = 1.5v 135mv; v ccp = 1.8v 90mv symbol parameter min typ max unit notes v cc vcc of core logic for 266pe mhz at low voltage 1.365 1.500 1.635 v 135 mv v cc,lp v cc when i cc < 300 a 1.365 1.500 1.705 v +205/-135 mv 1 v ccp v cc for cmos voltage references 1.710 1.800 1.890 v 1.8v 90 mv i cc i cc for v cc at core frequency @ 266pe mhz at low voltage 5.90 a note 4 i ccp current for v ccp 75 ma notes 2, 3, 4 i cc,sg processor stop grant and auto halt current 940 ma note 4 i cc,qs processor quick start and sleep current 630 ma note 4 i cc,dslp processor deep sleep leakage current 400 ma note 4 di cc /dt v cc power supply current slew rate 20 a/ s notes 5, 6 notes: 1. a higher v cc,max is allowed when the processor is in a low power state to enable high efficiency, low current modes in the power regulator. 2. i ccp is the current supply for the cmos voltage references. 3. not 100% tested. specified by design/characterization. 4. i ccx,max specifications are specified at v cc,max , v ccp,max and 100c and under maximum signal loading conditions. 5. based on simulations and averaged over the duration of any change in current. use to compute the maximum inductance and reaction time of the voltage regulator. this parameter is not tested. 6. maximum values specified by design/characterization at nominal v cc and v ccp . the signals on the mobile pentium ii processor system bus are included in the low power gtl+ signal group. these signals are specified to be terminated to v cc . the dc specifications for these signals are listed in table 3.10; the termination and reference voltage specifications for these signals are listed in table 3.11. the mobile pentium ii processor requires external termination and a v ref . refer to mobile pentium ? ii processor system bus layout guideline (order number 243672-001) for full details of system v tt and v ref requirements. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 21 table 3.10 low power gtl+ signal group dc specifications t case = 0 to t case,max ; v cc = 1.5v 115mv, v cc = 1.6v 135mv, or 1.5v 135mv; v ccp = 1.5v 90mv, or v ccp = 1.8v 90mv symbol parameter min max unit notes v il input low voltage C0.3 5 / 9 v tt C 0.2 v see table 3.11 1 v ih input high voltage 5 / 9 v tt + 0.2 v cc v note 1 v oh output high voltage v see v tt max in table 3.11 . r on output low drive strength 35 ohms i l leakage current for inputs 100 a note 2 i lo leakage current for outputs & i/os 30 a 366 mhz and below 3 i lo leakage current for outputs and i/os 100 a 400 mhz 3 notes: 1. v ref worst case, not nominal. noise on v ref should be accounted for. 2. (0 v in v cc ). 3. (0 v out v cc ). table 3.11. low power gtl+ bus dc specifications t case = 0 to t case,max ; v cc = 1.5v 115mv, v cc = 1.6v 135mv, or 1.5v 135mv; v ccp = 1.5v 90mv, or v ccp = 1.8v 90mv symbol parameter min typ max unit notes v tt bus termination voltage v cc,min v cc v cc,max v note 1 v ref input reference voltage 5 / 9 v tt C 2% 5 / 9 v tt 5 / 9 v tt + 2% v 2% 2 notes: 1. the intent is to use the same power supply for v cc and v tt . 2. v ref for the system logic should be created from v tt by a voltage divider. the cmos, open-drain and tap signals are designed to interface at v cmos to allow connection to other devices. bclk is a 2.5v clock. the dc mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 22 intel corporation specifications for these signals are listed in table 3.12. table 3.12 clock, apic, tap, cmos and open-drain signal group dc specifications for the mobile pentium? ii processor at 400 mhz t case = 0 to t case,max ; v cc = 1.5v 115mv, v ccp = 1.5v 90mv symbol parameter min max unit notes v il input low voltage C0.3 0.6 v v il,bclk input low voltage, bclk C0.3 0.7 v v ih input high voltage 1.135 1.615 v v ih,bclk input high voltage, bclk 1.8 2.625 v v ol output low voltage 0.4 v note 1 v oh output high voltage n/a 1.615 v all outputs are open-drain i ol output low current 14 ma i l leakage current for inputs, outputs, and i/os 100 a note 2 notes: 1. parameter measured at 14 ma. 2. (0 v in/out 1.615v). mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 23 table 3.13 clock, apic, tap, cmos and open-drain signal group dc specifications for the mobile pentium? ii processor at 366 mhz and below t case = 0 to t case,max ; v cc = 1.6v 135mv, or v cc = 1.5v 115mv, v ccp = 1.8v 90mv symbol parameter min max unit notes v il input low voltage C0.3 0.7 v v il,bclk input low voltage, bclk C0.3 0.7 v v ih input high voltage 1.700 2.625 v v ih,bclk input high voltage, bclk 1.800 2.625 v v ol output low voltage 0.4 v note 1 v oh output high voltage n/a 2.625 v all outputs are open-drain i ol output low current 14 ma i l input leakage current 100 a note 2 i lo output and i/o leakage current 30 a note 2 notes: 1. parameter measured at 14 ma. 2. (0 v in/out 2.625v). 3.6 ac specifications 3.6.1 system bus, clock, apic, tap, cmos and open-drain ac specifications table 3.14 through table 3.21 provide ac specifications associated with the mobile pentium ii processor. the ac specifications are divided into the following categories: table 3.14 contains the system bus clock specifications; table 3.15 contains the processor core frequencies; table 3.16 contains the low power gtl+ specifications; table 3.17 contains the cmos and open-drain signal groups specifications; table 3.18 contains timings for the reset conditions; table 3.19 contains the tap specifications; and table 3.20 and table 3.21 contain the power management timing specifications. all system bus ac specifications for the low power gtl+ signal group are relative to the rising edge of the bclk input at 1.25v. all low power gtl+ timings are referenced to v ref for both 0 and 1 logic levels unless otherwise specified. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 24 intel corporation table 3.14 system bus clock ac specifications 1 t case = 0 to t case,max ; v cc = 1.5v 115mv, v cc = 1.6v 135mv, or 1.5v 135mv; v ccp = 1.5v 90mv, or v ccp = 1.8v 90mv symbol parameter min typ max unit figure notes system bus frequency 66.67 mhz t1 bclk period 15 ns 3.3 note 2 t2 bclk period stability 250 ps notes 3, 4 t3 bclk high time 5.0 ns 3.3 @>1.8v t4 bclk low time 5.0 ns 3.3 @<0.7v t5 bclk rise time 0.175 0.875 ns 3.3 (0.9v C 1.6v) 4 t6 bclk fall time 0.175 0.875 ns 3.3 (1.6v C 0.9v) 4 notes: 1. all ac timings for low power gtl+ and cmos signals are referenced to the bclk rising edge at 1.25v. all cmos signals are referenced at v trip . 2. the bclk period allows a +0.5ns tolerance for clock driver variation. 3. not 100% tested. specified by design/characterization. 4. measured on the rising edge of adjacent bclks at 1.25v. the jitter present must be accounted for as a component of bclk skew between devices. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 25 table 3.15 valid mobile pentium ii processor frequencies t case = 0 to t case,max ; v cc = 1.5v 115mv, v cc = 1.6v 135mv, or 1.5v 135mv; v ccp = 1.5v 90mv, or v ccp = 1.8v 90mv bclk frequency (mhz) frequency multiplier core frequency (mhz) 66.67 4 266.67 66.67 9/2 300.00 66.67 5 333.33 66.67 11/2 366.67 66.67 6 400.00 note: because of the bus fraction locking scheme implemented in this processor, the frequency multiplier is internally set to a fixed value of six (6). the processor operates only at a core frequency of 400 mhz. table 3.16 low power gtl+ signal groups ac specifications 1 r tt = 120 terminated to v cc ; v ref = 5/9 v cc ; load = 0pf t case = 0 to t case,max ; v cc = 1.5v 115mv, v cc = 1.6v 135mv, or 1.5v 135mv; v ccp = 1.5v 90mv, or v ccp = 1.8v 90mv symbol parameter min max unit figure notes t7 low power gtl+ output valid delay 0.00 7.78 ns 3.4 t8 low power gtl+ input setup time 2.98 ns 3.5 notes 2, 3 t9 low power gtl+ input hold time 0.90 ns 3.5 note 4 t10 reset# pulse width 1 ms 3.6 3.7 note 5 notes: 1. all ac timings for low power gtl+ signals are referenced to the bclk rising edge at 1.25v. all low power gtl+ signals are referenced at v ref . 2. reset# can be asserted (active) asynchronously, but must be de-asserted synchronously. 3. specification is for a minimum 0.40v swing. 4. specification is for a maximum 1.0v swing. 5. after v cc , v ccp and bclk become stable and pwrgood is asserted. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 26 intel corporation table 3.17 cmos and open-drain signal groups ac specifications 1, 2 t case = 0 to t case,max ; v cc = 1.5v 115mv, v cc = 1.6v 135mv, or 1.5v 135mv; v ccp = 1.5v 90mv, or v ccp = 1.8v 90mv symbol parameter min max unit figure notes t14 cmos input pulse width, except pwrgood 2bclks 3.4 active and inactive states t15 pwrgood inactive pulse width 10 bclks 3.7 notes 3, 4 notes: 1. all ac timings for cmos and open-drain signals are referenced to the bclk rising edge at 1.25v. all cmos and open-drain signals are referenced at v trip . 2. minimum output pulse width on cmos outputs is 2 bclks. 3. when driven inactive, or after v cc , v ccp and bclk become stable. pwrgood must remain below v il,max from table 3.12 until all the voltage planes meet the voltage tolerance specifications in table 3.7, and bclk has met the bclk ac specifications in table 3.14 for at least 10 clock cycles. pwrgood must rise glitch-free and monotonically to v cmos . 4. if the bclk signal meets its ac specification within 150ns of turning on then the pwrgood inactive pulse width specification (t15) is waived and bclk may start after pwrgood is asserted. pwrgood must still remain below v il,max until all the voltage planes meet the voltage tolerance specifications. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 27 table 3.18 reset configuration ac specifications t case = 0 to t case,max ; v cc = 1.5v 115mv; v ccp = 1.5v 90mv symbol parameter min max unit figure notes t16 reset configuration signals (a[15:5]#, breq0#, flush#, init#, picd0) setup time 4bclks 3.5 3.6 before deassertion of reset# t17 reset configuration signals (a[15:5]#, breq0#, flush#, init#, picd0) hold time 220bclks 3.5 3.6 after clock that deasserts reset# t18 reset configuration signals (a20m#, ignne#, intr, nmi) setup time 1ms 3.7 before deassertion of reset# 1 t19 reset configuration signals (a20m#, ignne#, intr, nmi) delay time 5bclks 3.7 after assertion of reset# 2 t20 reset configuration signals (a20m#, ignne#, intr, nmi) hold time 220bclks 3.5 3.7 after clock that deasserts reset# notes: 1. at least 1 ms must pass after pwrgood rises above v ih,min from table 3.12, and bclk meets its ac timing specification, until reset# may be deasserted. 2. for a reset, the clock ratio defined by these signals must be a safe value (their final value or a lower multiplier) within this delay after reset# is asserted unless pwrgood is inactive (below v il,max ). mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 28 intel corporation table 3.19 tap signal ac specifications 1 t case = 0 to t case,max ; v cc = 1.5v 115mv; v ccp = 1.5v 90mv symbol parameter min max unit figure notes t30 tck frequency 16.67 mhz t31 tck period 60 ns 3.3 t32 tck high time 25.0 ns 3.3 1.135v 2 t33 tck low time 25.0 ns 3.3 0.60v 2 t34 tck rise time 5.0 ns 3.3 (0.60v-1.135v) 2,3 t35 tck fall time 5.0 ns 3.3 (1.135v-0.60v) 2,3 t36 trst# pulse width 40.0 ns 3.9 asynchronous 2 t37 tdi, tms setup time 5.0 ns 3.8 note 4 t38 tdi, tms hold time 14.0 ns 3.8 note 4 t39 tdo valid delay 1.0 10.0 ns 3.8 notes 5, 6 t40 tdo float delay 25.0 ns 3.8 notes 2, 5, 6 t41 all non-test outputs valid delay 2.0 25.0 ns 3.8 notes 5, 7, 8 t42 all non-test outputs float delay 25.0 ns 3.8 notes 2, 5, 7, 8 t43 all non-test inputs setup time 5.0 ns 3.8 notes 4, 7, 8 t44 all non-test inputs hold time 13.0 ns 3.8 notes 4, 7, 8 notes: 1. all ac timings for tap signals are referenced to the tck rising edge at v trip . all cmos signals are referenced at v trip . 2. not 100% tested. specified by design/characterization. 3. 1 ns can be added to the maximum tck rise and fall times for every 1 mhz below 16 mhz. 4. referenced to tck rising edge. 5. referenced to tck falling edge. 6. valid delay timing for this signal is specified into 150 terminated to v cmos and 0pf of external load. for real system timings these specifications must be derated for external capacitance at 105 ps/pf. 7. non-test outputs and inputs are the normal output or input signals (except tck, trst#, tdi, tdo and tms). these timings correspond to the response of these signals due to boundary scan operations. 8. during debug port operation use the normal specified timings rather than the tap signal timings. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 29 table 3.20 quick start/deep sleep ac specifications t case = 0 to t case,max ; v cc = 1.5v 115mv, v cc = 1.6v 135mv, or 1.5v 135mv; v ccp = 1.5v 90mv, or v ccp = 1.8v 90mv symbol parameter min max unit figure t45 stop grant cycle completion to clock stop 100 bclks 3.10 t46 stop grant cycle completion to input signals stable 0 ns 3.10 t47 deep sleep pll lock latency 30 s 3.10 t48 stpclk# hold time from pll lock 0 ns 3.10 t49 input signal hold time from stpclk# deassertion 8 bclks 3.10 note: input signals other than reset# and bpri# must be held constant in the quick start state. table 3.21 stop grant/sleep/deep sleep ac specifications t case = 0 to t case,max ; v cc = 1.5v 115mv, v cc = 1.6v 135mv, or 1.5v 135mv; v ccp = 1.5v 90mv, or v ccp = 1.8v 90mv symbol parameter min max unit figure t50 slp# signal hold time from stop grant cycle completion 100 bclks 3.11 t51 slp# assertion to input signals stable 0 ns 3.11 t52 slp# assertion to clock stop 10 bclks 3.11 t54 slp# hold time from pll lock 0 ns 3.11 t55 stpclk# hold time from slp# deassertion 10 bclks 3.11 t56 input signal hold time from slp# deassertion 10 bclks 3.11 note: input signals other than reset# must be held constant in the sleep state. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 30 intel corporation figure 3.3 through figure 3.11 are to be used in conjunction with table 3.14 through table 3.21. clk v ih v trip t h t l t p t r1 d0003-02 v il t f1 1.6v 0.9v t r2 t f2 notes: t r1 =t5, t r2 = t34 (rise time) t f1 =t6, t f2 = t35 (fall time) t h = t3, t32 (high time) t l = t4, t33 (low time) t p = t1, t31 (period) figure 3.3 generic clock waveform mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 31 clk signal t x t x t pw v valid valid d0004-00 notes: t x = t7, t11 (valid delay) t pw = t14 (pulse width) v= v ref for low power gtl+ signals; v trip for cmos, open-drain, and tap signal groups figure 3.4 valid delay timings clk signal v valid t h t s d0005-0 0 notes: t s = t8, t12 (setup time) t h = t9, t13 (hold time) v= v ref for low power gtl+ signals; v trip for cmos, open-drain, and tap signal groups figure 3.5 setup and hold timings mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 32 intel corporation bclk reset# configuration (a20m#, ignne#, intr, nmi) t v t x t t t u t z valid d0006-01 configuration (a[15:5], breq0#, flush#, init#, picd0) t w valid safe t y notes: t t = t9 (low power gtl+ input hold time) t u = t8 (low power gtl+ input setup time) t v = t10 (reset# pulse width) t w = t16 (reset configuration signals (a[15:5]#, breq0#, flush#, init#, picd0) setup time) t x = t17 (reset configuration signals (a[15:5]#, breq0#, flush#, init#, picd0) hold time) t20 (reset configuration signals (a20m#, ignne#, intr, nmi) hold time) t y = t19 (reset configuration signals (a20m#, ignne#, intr, nmi) delay time) t z = t18 (reset configuration signals (a20m#, ignne#, intr, nmi) setup time) figure 3.6 reset and configuration timings mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 33 bclk pwrgood reset# t a t b v , cc v ref d0007-01 v , ccp, v il,max configuration (a20m#, ignne#, intr, nmi) t c valid ratio v ih,min notes: t a = t15 (pwrgood inactive pulse width) t b = t10 (reset# pulse width) t c = t20 (reset configuration signals (a20m#, ignne#, intr, nmi) hold time) figure 3.7 power-on reset timings mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 34 intel corporation tck tdi, tms input signals tdo output signals v trip t v t w t r t s t x t u t y t z d0008-02 notes: t r = t43 (all non-test inputs setup time) t s = t44 (all non-test inputs hold time) t u = t40 (tdo float delay) t v = t37 (tdi, tms setup time) t w = t38 (tdi, tms hold time) t x = t39 (tdo valid delay) t y = t41 (all non-test outputs valid delay) t z = t42 (all non-test outputs float delay) figure 3.8 test timings (boundary scan) trst# v trip t q d0009-02 note: t q = t36 (trst# pulse width) figure 3.9 test reset timings mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 35 t w stpgnt running running bclk stpclk# cpu bus slp# compatibility signals changing normal quick start deep sleep quick start normal frozen t v t y t z t x v0010-00 notes: t v = t45 (stop grant acknowledge bus cycle completion to clock shut off delay) t w = t46 (setup time to input signal hold requirement) t x = t47 (deep sleep pll lock latency) t y = t48 (pll lock to stpclk# hold time) t z = t49 (input signal hold time) figure 3.10 quick start/deep sleep timing mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 36 intel corporation t u stpgnt running bclk stpclk# cpu bus slp# compatibility signals frozen changing normal stop grant sleep deep sleep sleep stop grant normal running t t t v t y t z t w t x v0011-00 changing notes: t t = t50 (stop grant acknowledge bus cycle completion to slp# assertion delay) t u = t51 (setup time to input signal hold requirement) t v = t52 (slp# assertion to clock shut off delay) t w = t47 (deep sleep pll lock latency) t x = t54 (slp# hold time) t y = t55 (stpclk# hold time) t z = t56 (input signal hold time) figure 3.11 stop grant/sleep/deep sleep timing mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 37 4. system signal simulations many scenarios have been simulated to generate a set of low power gtl+ processor system bus layout guidelines which are available in the mobile pentium ? ii processor system bus layout guideline (order number 243672-001). systems must be simulated using the ibis models to determine if they are compliant with this specification. there are different ibis models for the 400 mhz and for the 366 mhz and below 4.1 system bus clock (bclk) signal quality specifications table 4.1 and figure 4.1 show the signal quality for the system bus clock (bclk) signal as measured at the processor. the timings illustrated in figure 4.1 are taken from table 3.14. bclk is a 2.5v clock. table 4.1 bclk signal quality specifications symbol parameter min max unit figure notes v1 v il,bclk 0.7 v 4.1 note 1 v2 v ih,bclk 1.8 v 4.1 note 1 v3 v in absolute voltage range C0.7 3.5 v 4.1 undershoot, overshoot 2 v3 v in absolute voltage range C0.8 3.5 v 4.1 undershoot, overshoot 3 v4 rising edge ringback 1.8 v 4.1 absolute value 4 v5 falling edge ringback 0.7 v 4.1 absolute value 4 bclk rising/falling slew rate 0.8 4 v/ns 4.1 notes: 1. bclk must rise/fall monotonically between v il,bclk and v ih,bclk . 2. 400 mhz processor only. 3. 366 mhz and below. 4. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bclk signal can dip back to after passing the v ih,bclk (rising) or v il,bclk (falling) voltage limits. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 38 intel corporation v1 v3 v2 v4 v3 v5 v0012-00 t3 t6 t4 t5 figure 4.1 bclk generic clock waveform 4.2 low power gtl+ signal quality specifications table 4.2 and figure 4.2 illustrate the gtl+ signal quality specifications for the mobile pentium ii processor. refer to the pentium ? ii processor developers manual for the gtl+ buffer specification. the mobile pentium? ii processor at 400 mhz also has additional specifications on maximum allowable overshoot and undershoot for a given duration of time, as listed in table 4.3. contact your intel field sales representative for a copy of the overshoot_checker tool. overshoot_checker determines if a specific waveform meets the overshoot/undershoot specification. figure 4.3 shows the overshoot/ undershoot waveform. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 39 table 4.2 low power gtl+ signal group ringback specification for the mobile pentium? ii processor symbol parameter min unit figure notes overshoot 100 mv 4.2 notes 1, 2 minimum time at high 1 ns 4.2 notes 1, 2 amplitude of ringback -100 mv 4.2 notes 1, 2, 3 final settling voltage 100 mv 4.2 notes 1, 2 duration of sequential ringback n/a ns 4.2 notes 1, 2 notes: 1. specified for the edge rate of 0.3 C 0.8 v/ns. see figure 4.2 for the generic waveform. 2. all values determined by design/characterization. 3. ringback below v ref +100 mv is not authorized during low to high transitions. ringback above v ref - 100mv is not authorized during high to low transitions. v ref +0.2v time v ref -0.2v v ref v start clock v il,bclk v ih,bclk v0014-00 note: high-to-low case is analogous. figure 4.2 gtl+ receiver ringback tolerance mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 40 intel corporation table 4.3. gtl+ signal group overshoot/undershoot tolerance at the processor core 1, 4, 5 for the mobile pentium? ii processor at 400 mhz pulse duration allowed overshoot 2 allowed undershoot 3 0.1 ns 2.0v -0.35v 0.3 ns 1.9v -0.25v 1.0 ns 1.8v -0.15v notes: 1. under no circumstances should the gtl+ signal voltage ever exceed 2.0v maximum with respect to ground or -2.0v minimum with respect to v cct (i.e., v cct - 2.0v) under operating conditions. 2. ring-backs below v cct cannot be subtracted from overshoots. lesser undershoot does not allocate longer or larger overshoot. 3. ring-backs above ground cannot be subtracted from undershoots. lesser overshoot does not allocate longer or larger undershoot. 4. system designers are encouraged to follow intel provided gtl+ layout guidelines. 5. all values are specified by design characterization, and are not tested. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 41 vtt 2.0v max 1.9v 1.8v vss time dependent overshoot time dependent undershoot -.15v - .25v -.35v min .1ns .3ns 1ns .1ns .3ns 1ns note: the total overshoot/undershoot budget for one clock cycle is fully consumed by the , or waveforms. figure 4.3 maximum acceptable gtl+ overshoot/undershoot waveform for the mobile pentium? ii processor at 400 mhz 4.3 non-low power gtl+ signal quality specifications signals driven to the mobile pentium ii processor should meet signal quality specifications to ensure that the processor reads data properly and that incoming signals do not affect the long-term reliability of the processor. there are three signal quality parameters defined: overshoot/ undershoot, ringback and settling limit. the ringback and settling limit signal quality parameters are shown in figure 4.4 for non-gtl+ signal groups. the overshoot and undershoot specifications for non-gtl+ signals are the same as for gtl+ signals; see section 4.2. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 42 intel corporation v lo v cmos v ss time settling limit settling limit undershoot overshoot rising-edge ringback falling-edge ringback v0015-01 figure 4.4 non-gtl+ signal ringback and settling limit 4.3.1 overshoot and undershoot guidelines overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below v ss . the overshoot/undershoot guideline limits transitions beyond v cc or v ss due to the fast signal edge rates. the processor can be damaged by repeated overshoot events on v cmos tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). however, excessive ringback is the dominant detrimental system timing effect resulting from overshoot/undershoot (i.e., violating the overshoot/undershoot guideline will make it difficult to satisfy the ringback specification). the overshoot/undershoot guideline is 0.7v for the 400 mhz, 0.8v for the 366 mhz and below and assumes the absence of diodes on the input. these guidelines should be verified in simulations without the on-chip esd protection diodes present because the diodes will begin clamping the v cmos tolerant signals beginning at approximately 1.25v above v cc and 0.5v below v ss . if the signals do not reach the clamping voltage, then this will not be an issue. a mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 43 system should not rely on the diodes for overshoot/undershoot protection as this will negatively affect the life of the components and make meeting the ringback specification very difficult. 4.3.1 ringback specification ringback refers to the amount of reflection seen after a signal has switched. the ringback specification is the voltage to which the signal rings back after achieving its maximum absolute value. excessive ringback can cause false signal detection or extend the propagation delay. the ringback specification applies to the input signal of each receiving agent. violations of the signal ringback specification are not allowed under any circumstances for the non-gtl+ signals. ringback can be simulated with or without the input protection diodes that can be added to the input buffer model. however, signals that reach the clamping voltage should be evaluated further. see table 4.4 for the signal ringback specifications for non-gtl+ signals. 4.3.2 settling limit guideline settling limit defines the maximum amount of ringing at the receiving signal that a signal may reach before its next transition. the amount allowed is 10% of the total signal swing (v hi C v lo ) above and below its final value. a signal should be within the settling limits of its final value, when either in its high state or low state, before its next transition. signals that are not within their settling limit before transitioning are at risk of unwanted oscillations that could jeopardize signal integrity. simulations to verify settling limit may be done either with or without the input protection diodes present. violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions. table 4.4 signal ringback specifications for non-gtl+ signals for the mobile pentium? ii processor at 400 mhz input signal group transition maximum ringback (with input diodes present) figure non-gtl+ signals 0 1 1.135 v 4.4 non-gtl+ signals 1 0 0.600 v 4.4 table 4.5 signal ringback specifications for non-gtl+ signals for the mobile pentium? ii processor at 366 mhz and below input signal group transition maximum ringback (with input diodes present) figure non-gtl+ signals 0 1 1.700 v 4.4 non-gtl+ signals 1 0 0.700 v 4.4 mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 44 intel corporation 5. mechanical specifications the mobile pentium? ii processor are available in a ppga-b615 package (also known as micro-pga) or in a pbga-b615 package (also known as bga). the back of the processor die exposed on top of both packages. this section contains information describing the packages and the signal pin assignments. 5.1 dimensions of the micro-pga package the micro-pga dimensions are given in table 5.1, and shown in figure 5.1 and figure 5.2. for component handling, the substrate may only be contacted within the region between the keepout outline and the edge of the substrate. table 5.1 micro-pga package mechanical specifications symbol parameter min max unit a overall height, t op of die to seating plane of the interposer 3.23 3.83 mm a 1 pin length 1.25 ref mm a 2 die height 0.854 ref mm b pin diameter 0.30 ref mm d die substrate width 30.85 31.15 mm d 1 die width 10.36 ref mm d 2 package width 32.60 ref mm e die substrate length 34.85 35.15 mm e 1 die length 17.36 ref mm e 2 package length 36.80 ref mm e pin pitch 1.27 pin tip radial true position <=1.27 n pin count 615 each s 1 pin row a to short edge of interposer 2.220 ref mm s 2 pin column 1 to long edge of interposer 1.415 ref mm p die allowable pressure on the die for thermal solution 689 kpa w package weight 7.5 ref grams mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 45 note: dimensions in parentheses are for reference only. all dimensions are in millimeters. figure 5.1 micro-pga package-top and side view mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 46 intel corporation note: dimensions in parentheses are for reference only. all dimensions are in millimeters. figure 5.2 micro-pga package - bottom view 5.2 dimensions of the bga package the mechanical specifications for the surface-mount package are provided in table 5.2. figure 5.3 shows the top and side views of the surface-mount package and, and figure 5.4 shows the bottom view of the surface-mount package. for component handling, the substrate may only be contacted within the shaded region between the keepout outline and the edge of the substrate. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 47 table 5.2 surface-mount bga package specifications symbol parameter min max unit a overall height, as delivered (use this for 5.2) 2.29 2.79 mm a 1 substrate height, as delivered 1.50 ref mm a 2 die height 0.854 ref mm b ball diameter 0.78 ref mm d package width 30.85 31.15 mm d 1 die width 10.36 ref mm e package length 34.85 35.15 mm e ball pitch 1.27 mm e 1 die length 17.36 ref mm n ball count 615 each s 1 outer ball center to short edge of substrate 1.625 ref mm s 2 outer ball center to long edge of substrate 0.895 ref mm p die allowable pressure on the die for thermal solution 689 kpa w package weight 3.71 4.52 grams mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 48 intel corporation d 1 e 1 v0026-00 (2x 1.800) (2x 0.57) (? 0.65) (? 1.15) d (2x 2.032) e a a 1 a 2 substrate keepout outline die (2x 1.50) (5.0 typ) (7.0 typ) ink swatch ink swatch 0.20 ref note: dimensions in parentheses are for reference only. all dimensions are in millimeters. figure 5.3 surface-mount bga package - top and side view mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 49 af ae ad ac ab aa y w v u t r p n m l h g f e d c 3 4 5 6 9 10111213 15161718192021222324 b 2 v0025-01 k j a 7 8 1 14 s 2 e ?b e s 1 note: dimensions in parentheses are for reference only. all dimensions are in millimeters. figure 5.4 surface-mount bga package - bottom view 5.3 signal listings figure 5.5 is a topside view of the ball/pin map of the mobile pentium? ii processor with the voltage pins/balls called out. table 5.3 lists the signals in pin/ball number order. table 5.4 and table 5.5 list the signals in signal name order. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 50 intel corporation v0024-04 vcc other vccp vss analog decou p lin g nc vss d16# d18# vss d3# d5# vss vss d0# vss nc nc vss nc vss vss a34# a26# vss a29# vss vss vss vss d31# d26# d13# d7# d2# d17# d15# d6# nc nc nc nc nc nc testhi a24# a30# a22# a19# a35# edg ctrln vss d35# d29# d27# d24# d21# d19# d14# d10# d1# d4# nc nc nc nc nc berr# reset# a33# a31# a17# a25# nc nc vss d33# vss d28# d32# vss d22# d20# vss d9# vref vss nc nc vss vref a27# vss a20# a23# vss testlo testlo vss a28# nc d39# d34# vref vss d25# d23# d30# d11# d12# d8# nc nc nc a32# a18# vref a21# nc vss testlo a13# a12# a16# vccp nc d43# d36# d37 a10# a5# a15# a3# a11# nc d44# vss d38 a14# vss a6# a8# d49# d51# d42# d45# ap0# a9# a4# a7# d40# d52# d41# d47# d48# vref ap1# rsp# bnr# testhi3 vss d57# vss vss d59# testhi3 vss vss testhi3 vss d53# d46# d55# vref d54# testhi req0# req4# bpri# req1# d60# d58# d50# d56# d61# trdy# lock# testhi3 req2# defer# vss d62# d63# vss dep7# vref vss hitm# req3# vss vss dep6# dep5# dep3# dep0# hit# drdy# rp# dbsy# vss dep4# dep2# dep1# vref bpm1# pw rgood rs1# rs2# rs0# breq0# vss binit# prdy# vss bp3# slp# vss thermda ads# vss bpm0# bp2# testhi3 picclk picd1 tdi nc thermdc vccp aerr# testhi preq# intr nc vccp tms nc bsel picd0 vss vss nc vccp vss vss trst# vss vccp vccp nc nc testlo ferr# smi# tck vss nmi nc nc nc nc nc ierr# init# a20m# stpclk# nc nc nc nc nc nc nc ignne# tdo vss vss nc vtol nc testlo nc testhi2 flush# nc testhi2 vccp vss nc vss vss vss vss bclk vss nc 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pll1 pll2 nc nc nc nc nc nc nc nc nc nc vss vss vss vss vss nc nc nc vcc vss vcc vss vcc vss vcc vss nc nc nc nc nc nc vss vcc vss vcc vss vcc vss vcc nc nc nc nc nc nc vcc vss vcc vss vcc vss vcc vss nc nc nc nc nc nc vss vcc vss vcc vss vcc vss vcc nc nc nc nc nc nc vcc vss vcc vss vcc vss vcc vss nc nc nc nc nc nc vss vcc vss vcc vss vcc vss vcc nc nc nc nc nc nc vcc vss vcc vss vcc vss vcc vss nc nc nc nc nc nc vss vcc vss vcc vss vcc vss vcc nc nc nc nc nc nc vcc vss vcc vss vcc vss vcc vss nc nc nc nc nc nc vss vcc vss vcc vss vcc vss vcc nc nc nc nc nc nc vcc vss vcc vss vcc vss vcc vss nc nc nc nc nc nc vss vcc vss vcc vss vcc vss vcc nc nc nc nc nc nc vcc vss vcc vss vcc vss vcc vss nc nc nc nc nc nc vss vcc vss vcc vss vcc vss vcc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af vcc vss vccp figure 5.5 pin/ball map - top view mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 51 table 5.3 signal listing in order by pin/ball number no. signal name no. signal name no. signal name no. signal name a2 vss b8 testhi c14 nc d20 vss a3 vss b9 nc c15 d4# d21 d32# a4 a29# b10 nc c16 d1# d22 d28# a5 vss b11 nc c17 d10# d23 vss a6 a26# b12 nc c18 d14# d24 d33# a7 a34# b13 nc c19 d19# e1 a16# a8 vss b14 nc c20 d21# e2 a12# a9 vss b15 d6# c21 d24# e3 a13# a10 nc b16 d15# c22 d27# e4 testlo a11 vss b17 d17# c23 d29# e5 vss a12 nc b18 d2# c24 d35# e6 nc a13 nc b19 d7# d1 a28# e7 a21# a14 vss b20 d13# d2 vss e8 vref a15 d0# b21 d26# d3 testlo e9 a18# a16 vss b22 d31# d4 testlo e10 a32# a17 vss b23 vss d5 vss e11 nc a18 d5# b24 vss d6 a23# e12 nc a19 d3# c1 vss d7 a20# e13 nc a20 vss c2 nc d8 vss e14 d8# a21 d18# c3 nc d9 a27# e15 d12# a22 d16# c4 a25# d10 vref e16 d11# a23 vss c5 a17# d11 vss e17 d30# a24 nc c6 a31# d12 nc e18 d23# b1 vss c7 a33# d13 nc e19 d25# b2 edgctrln c8 reset# d14 vss e20 vss b3 a35# c9 berr# d15 vref e21 vref b4 a19# c10 nc d16 d9# e22 d34# b5 a22# c11 nc d17 vss e23 d39# b6 a30# c12 nc d18 d20# e24 nc b7 a24# c13 nc d19 d22# f1 a11# mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 52 intel corporation table 5.3 signal listing in order by pin/ball number no. signal name no. signal name no. signal name no. signal name f2 a3# g8 nc h15 vcc j21 d47# f3 a15# g9 vss h16 vss j22 d41# f4 a5# g10 vcc h17 nc j23 d52# f5 a10# g11 vss h18 nc j24 d40# f6 nc g12 vcc h19 nc k1 vss f7 nc g13 vss h20 d45# k2 testhi3 f8 nc g14 vcc h21 d42# k3 vss f9 nc g15 vss h22 d51# k4 vss f10 nc g16 vcc h23 d49# k5 testhi3 f11 nc g17 nc j1 testhi3 k6 nc f12 nc g18 nc j2 bnr# k7 nc f13 nc g19 nc j3 rsp# k8 nc f14 nc g20 d38# j4 ap1# k9 vcc f15 nc g21 vss j5 vref k10 vss f16 nc g22 d44# j6 nc k11 vcc f17 nc g23 nc j7 nc k12 vss f18 nc h2 a7# j8 nc k13 vcc f19 nc h3 a4# j9 vss k14 vss f20 d37# h4 a9# j10 vcc k15 vcc f21 d36# h5 ap0# j11 vss k16 vss f22 d43# h6 nc j12 vcc k17 nc f23 nc h7 nc j13 vss k18 nc f24 vccp h8 nc j14 vcc k19 nc g2 a8# h9 vcc j15 vss k20 d59# g3 a6# h10 vss j16 vcc k21 vss g4 vss h11 vcc j17 nc k22 vss g5 a14# h12 vss j18 nc k23 d57# g6 nc h13 vcc j19 nc k24 vss g7 nc h14 vss j20 d48# l1 req1# mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 53 table 5.3 signal listing in order by pin/ball number no. signal name no. signal name no. signal name no. signal name l2 bpri# m8 nc n14 vcc p20 dep0# l3 req4# m9 vcc n15 vss p21 dep3# l4 req0# m10 vss n16 vcc p22 dep5# l5 testhi m11 vcc n17 nc p23 dep6# l6 nc m12 vss n18 nc p24 vss l7 nc m13 vcc n19 nc r1 breq0# l8 nc m14 vss n20 dep7# r2 rs0# l9 vss m15 vcc n21 vss r3 rs2# l10 vcc m16 vss n22 d63# r4 rs1# l11 vss m17 nc n23 d62# r5 pwrgood l12 vcc m18 nc n24 vss r6 nc l13 vss m19 nc p1 vss r7 nc l14 vcc m20 d61# p2 dbsy# r8 nc l15 vss m21 d56# p3 rp# r9 vss l16 vcc m22 d50# p4 drdy# r10 vcc l17 nc m23 d58# p5 hit# r11 vss l18 nc m24 d60# p6 nc r12 vcc l19 nc n1 vss p7 nc r13 vss l20 d54# n2 req3# p8 nc r14 vcc l21 vref n3 hitm# p9 vcc r15 vss l22 d55# n4 vss p10 vss r16 vcc l23 d46# n5 vref p11 vcc r17 nc l24 d53# n6 nc p12 vss r18 nc m1 defer# n7 nc p13 vcc r19 nc m2 req2# n8 nc p14 vss r20 bpm1# m3 testhi3 n9 vss p15 vcc r21 vref m4 lock# n10 vcc p16 vss r22 dep1# m5 trdy# n11 vss p17 nc r23 dep2# m6 nc n12 vcc p18 nc r24 dep4# m7 nc n13 vss p19 nc t1 vss mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 54 intel corporation table 5.3 signal listing in order by pin/ball number no. signal name no. signal name no. signal name no. signal name t2 ads# u8 nc v15 vcc w23 picd0 t3 thermda u9 vss v16 vss y1 vss t4 vss u10 vcc v17 nc y2 tck t5 slp# u11 vss v18 nc y3 smi# t6 nc u12 vcc v19 nc y4 ferr# t7 nc u13 vss v20 nc y5 testlo t8 nc u14 vcc v21 intr y6 nc t9 vcc u15 vss v22 preq# y7 nc t10 vss u16 vcc v23 testhi y8 nc t11 vcc u17 nc w2 trst# y9 vcc t12 vss u18 nc w3 vss y10 vss t13 vcc u19 nc w4 vss y11 vcc t14 vss u20 picd1 w5 vccp y12 vss t15 vcc u21 picclk w6 nc y13 vcc t16 vss u22 testhi3 w7 nc y14 vss t17 nc u23 bp2# w8 nc y15 vcc t18 nc u24 bpm0# w9 vss y16 vss t19 nc v2 bsel w10 vcc y17 nc t20 bp3# v3 nc w11 vss y18 nc t21 vss v4 tms w12 vcc y19 nc t22 prdy# v5 vccp w13 vss y20 nc t23 binit# v6 nc w14 vcc y21 nc t24 vss v7 nc w15 vss y22 vccp u1 aerr# v8 nc w16 vcc y23 vccp u2 vccp v9 vcc w17 nc y24 vss u3 thermdc v10 vss w18 nc aa1 stpclk# u4 nc v11 vcc w19 nc aa2 a20m# u5 tdi v12 vss w20 nc aa3 init# u6 nc v13 vcc w21 vss aa4 ierr# u7 nc v14 vss w22 vss aa5 nc mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 55 table 5.3 signal listing in order by pin/ball number no. signal name no. signal name no. signal name no. signal name aa6 nc ab12 nc ac18 nc ad24 nc aa7 nc ab13 nc ac19 nc ae1 vss aa8 nc ab14 nc ac20 nc ae2 vss aa9 nc ab15 nc ac21 vtol ae3 vss aa10 nc ab16 nc ac22 nc ae4 vss aa11 nc ab17 nc ac23 vss ae5 vss aa12 nc ab18 nc ac24 vss ae6 vss aa13 nc ab19 nc ad1 vss ae7 vss aa14 nc ab20 nc ad2 vccp ae8 nc aa15 nc ab21 nc ad3 vcc ae9 nc aa16 nc ab22 nc ad4 testhi2 ae10 nc aa17 nc ab23 nc ad5 nc ae11 nc aa18 nc ab24 nc ad6 nc ae12 nc aa19 nc ac1 flush# ad7 nc ae13 nc aa20 nc ac2 testhi2 ad8 nc ae14 nc aa21 nc ac3 nc ad9 nc ae15 nc aa22 nc ac4 vss ad10 nc ae16 nc aa23 nc ac5 testlo ad11 nc ae17 nc aa24 nmi ac6 nc ad12 nc ae18 nc ab1 tdo ac7 nc ad13 nc ae19 nc ab2 ignne# ac8 nc ad14 nc ae20 nc ab3 nc ac9 nc ad15 nc ae21 nc ab4 vccp ac10 nc ad16 nc ae22 nc ab5 nc ac11 nc ad17 nc ae23 nc ab6 nc ac12 nc ad18 nc ae24 nc ab7 nc ac13 nc ad19 nc af1 nc ab8 nc ac14 nc ad20 nc af2 vss ab9 nc ac15 nc ad21 nc af3 bclk ab10 nc ac16 nc ad22 nc af4 vss ab11 nc ac17 nc ad23 nc af5 pll2 mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 56 intel corporation table 5.3 signal listing in order by pin/ball number no. signal name no. signal name no. signal name no. signal name af6 pll1 af11 nc af16 nc af21 nc af7 vss af12 nc af17 nc af22 nc af8 nc af13 nc af18 nc af23 nc af9 nc af14 nc af19 nc af24 nc af10 nc af15 nc af20 nc mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 57 table 5.4 signal listing in order by signal name no. signal name signal buffer type no. signal name signal buffer type f2 a3# low power gtl+ i/o c7 a33# low power gtl+ i/o h3 a4# low power gtl+ i/o a7 a34# low power gtl+ i/o f4 a5# low power gtl+ i/o b3 a35# low power gtl+ i/o g3 a6# low power gtl+ i/o aa2 a20m# cmos input h2 a7# low power gtl+ i/o t2 ads# low power gtl+ i/o g2 a8# low power gtl+ i/o u1 aerr# low power gtl+ i/o h4 a9# low power gtl+ i/o h5 ap0# low power gtl+ i/o f5 a10# low power gtl+ i/o j4 ap1# low power gtl+ i/o f1 a11# low power gtl+ i/o af3 bclk processor clock input e2 a12# low power gtl+ i/o c9 berr# low power gtl+ i/o e3 a13# low power gtl+ i/o t23 binit# low power gtl+ i/o g5 a14# low power gtl+ i/o j2 bnr# low power gtl+ i/o f3 a15# low power gtl+ i/o u23 bp2# low power gtl+ i/o e1 a16# low power gtl+ i/o t20 bp3# low power gtl+ i/o c5 a17# low power gtl+ i/o u24 bpm0# low power gtl+ i/o e9 a18# low power gtl+ i/o r20 bpm1# low power gtl+ i/o b4 a19# low power gtl+ i/o l2 bpri# low power gtl+ input d7 a20# low power gtl+ i/o r1 breq0# low power gtl+ i/o e7 a21# low power gtl+ i/o v2 bsel cmos input b5 a22# low power gtl+ i/o a15 d0# low power gtl+ i/o d6 a23# low power gtl+ i/o c16 d1# low power gtl+ i/o b7 a24# low power gtl+ i/o b18 d2# low power gtl+ i/o c4 a25# low power gtl+ i/o a19 d3# low power gtl+ i/o a6 a26# low power gtl+ i/o c15 d4# low power gtl+ i/o d9 a27# low power gtl+ i/o a18 d5# low power gtl+ i/o d1 a28# low power gtl+ i/o b15 d6# low power gtl+ i/o a4 a29# low power gtl+ i/o b19 d7# low power gtl+ i/o b6 a30# low power gtl+ i/o e14 d8# low power gtl+ i/o c6 a31# low power gtl+ i/o d16 d9# low power gtl+ i/o e10 a32# low power gtl+ i/o c17 d10# low power gtl+ i/o mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 58 intel corporation table 5.4 signal listing in order by signal name no. signal name signal buffer type no. signal name signal buffer type e16 d11# low power gtl+ i/o j22 d41# low power gtl+ i/o e15 d12# low power gtl+ i/o h21 d42# low power gtl+ i/o b20 d13# low power gtl+ i/o f22 d43# low power gtl+ i/o c18 d14# low power gtl+ i/o g22 d44# low power gtl+ i/o b16 d15# low power gtl+ i/o h20 d45# low power gtl+ i/o a22 d16# low power gtl+ i/o l23 d46# low power gtl+ i/o b17 d17# low power gtl+ i/o j21 d47# low power gtl+ i/o a21 d18# low power gtl+ i/o j20 d48# low power gtl+ i/o c19 d19# low power gtl+ i/o h23 d49# low power gtl+ i/o d18 d20# low power gtl+ i/o m22 d50# low power gtl+ i/o c20 d21# low power gtl+ i/o h22 d51# low power gtl+ i/o d19 d22# low power gtl+ i/o j23 d52# low power gtl+ i/o e18 d23# low power gtl+ i/o l24 d53# low power gtl+ i/o c21 d24# low power gtl+ i/o l20 d54# low power gtl+ i/o e19 d25# low power gtl+ i/o l22 d55# low power gtl+ i/o b21 d26# low power gtl+ i/o m21 d56# low power gtl+ i/o c22 d27# low power gtl+ i/o k23 d57# low power gtl+ i/o d22 d28# low power gtl+ i/o m23 d58# low power gtl+ i/o c23 d29# low power gtl+ i/o k20 d59# low power gtl+ i/o e17 d30# low power gtl+ i/o m24 d60# low power gtl+ i/o b22 d31# low power gtl+ i/o m20 d61# low power gtl+ i/o d21 d32# low power gtl+ i/o n23 d62# low power gtl+ i/o d24 d33# low power gtl+ i/o n22 d63# low power gtl+ i/o e22 d34# low power gtl+ i/o p2 dbsy# low power gtl+ i/o c24 d35# low power gtl+ i/o m1 defer# low power gtl+ input f21 d36# low power gtl+ i/o p20 dep0# low power gtl+ i/o f20 d37# low power gtl+ i/o r22 dep1# low power gtl+ i/o g20 d38# low power gtl+ i/o r23 dep2# low power gtl+ i/o e23 d39# low power gtl+ i/o p21 dep3# low power gtl+ i/o j24 d40# low power gtl+ i/o r24 dep4# low power gtl+ i/o mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 59 table 5.4 signal listing in order by signal name no. signal name signal buffer type no. signal name signal buffer type p22 dep5# low power gtl+ i/o r2 rs0# low power gtl+ input p23 dep6# low power gtl+ i/o r4 rs1# low power gtl+ input n20 dep7# low power gtl+ i/o r3 rs2# low power gtl+ input p4 drdy# low power gtl+ i/o j3 rsp# low power gtl+ input b2 edgctrln low power gtl+ control t5 slp# cmos input y4 ferr# open drain output y3 smi# cmos input ac1 flush# cmos input aa1 stpclk# cmos input p5 hit# low power gtl+ i/o y2 tck jtag clock input n3 hitm# low power gtl+ i/o u5 tdi jtag input aa4 ierr# open drain output ab1 tdo jtag output ab2 ignne# cmos input b8 testhi gtl+ test input aa3 init# cmos input l5 testhi gtl+ test input v21 intr cmos input v23 testhi gtl+ test input m4 lock# low power gtl+ i/o ac2 testhi2 cmos test input aa24 nmi cmos input ad4 testhi2 cmos test input u21 picclk apic clock input j1 testhi3 gtl+ test input w23 picd0 open drain i/o k2 testhi3 gtl+ test input u20 picd1 open drain i/o k5 testhi3 gtl+ test input af6 pll1 pll analog voltage m3 testhi3 gtl+ test input af5 pll2 pll analog voltage u22 testhi3 gtl+ test input t22 prdy# low power gtl+ output d3 testlo test input v22 preq# cmos input d4 testlo test input r5 pwrgood cmos input e4 testlo test input l4 req0# low power gtl+ i/o y5 testlo test input l1 req1# low power gtl+ i/o ac5 testlo test input m2 req2# low power gtl+ i/o t3 thermda thermal diode anode n2 req3# low power gtl+ i/o u3 thermdc thermal diode cathode l3 req4# low power gtl+ i/o v4 tms jtag input c8 reset# low power gtl+ input m5 trdy# low power gtl+ input p3 rp# low power gtl+ i/o j5 vref gtl+ reference voltage mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 60 intel corporation table 5.4 signal listing in order by signal name no. signal name signal buffer type no. signal name signal buffer type d10 vref gtl+ reference voltage l21 vref gtl+ reference voltage d15 vref gtl+ reference voltage n5 vref gtl+ reference voltage e8 vref gtl+ reference voltage r21 vref gtl+ reference voltage e21 vref gtl+ reference voltage ac21 vtol voltage tolerance w2 trst# jtag input note: except for bclk, the cmos signals are 1.5v tolerant for 400 mhz; and 2.5v tolerant for 366 mhz and below. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 61 table 5.5 voltage and no-connect ball/pin locations signal name ball numbers nc a10, a12, a13, a24, b9, b10, b11, b12, b13, b14, c2, c3, c10, c11, c12, c13, c14, d12, d13, e6, e11, e12, e13, e24, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, f16, f17, f18, f19, f23, g6, g7, g8, g17, g18, g19, g23, h6, h7, h8, h17, h18, h19, j6, j7, j8, j17, j18, j19, k6, k7, k8, k17, k18, k19, l6, l7, l8, l17, l18, l19, m6, m7, m8, m17, m18, m19, n6, n7, n8, n17, n18, n19, p6, p7, p8, p17, p18, p19, r6, r7, r8, r17, r18, r19, t6, t7, t8, t17, t18, t19, u4, u6, u7, u8, u17, u18, u19, v3, v6, v7, v8, v17, v18, v19, v20, w6, w7, w8, w17, w18, w19, w20, y6, y7, y8, y17, y18, y19, y20, y21, aa5, aa6, aa7, aa8, aa9, aa10, aa11, aa12, aa13, aa14, aa15, aa16, aa17, aa18, aa19, aa20, aa21, aa22, aa23, ab3, ab5, ab6, ab7, ab8, ab9, ab10, ab11, ab12, ab13, ab14, ab15, ab16, ab17, ab18, ab19, ab20, ab21, ab22, ab23, ab24, ac3, ac6, ac7, ac8, ac9, ac10, ac11, ac12, ac13, ac14, ac15, ac16, ac17, ac18, ac19, ac20, ac22, ad5, ad6, ad7, ad8, ad9, ad10, ad11, ad12, ad13, ad14, ad15, ad16, ad17, ad18, ad19, ad20, ad21, ad22, ad23, ad24, ae8, ae9, ae10, ae11, ae12, ae13, ae14, ae15, ae16, ae17, ae18, ae19, ae20, ae21, ae22, ae23, ae24, af1, af8, af9, af10, af11, af12, af13, af14, af15, af16, af17, af18, af19, af20, af21, af22, af23, af24 vcc g10, g12, g14, g16, h9, h11, h13, h15, j10, j12, j14, j16, k9, k11, k13, k15, l10, l12, l14, l16, m9, m11, m13, m15, n10, n12, n14, n16, p9, p11, p13, p15, r10, r12, r14, r16, t9, t11, t13, t15, u10, u12, u14, u16, v9, v11, v13, v15, w10, w12, w14, w16, y9, y11, y13, y15, ad3 vccp f24, u2, v5, w5, y22, y23, ab4, ad2 vss a2, a3, a5, a8, a9, a11, a14, a16, a17, a20, a23, b1, b23, b24, c1, d2, d5, d8, d11, d14, d17, d20, d23, e5, e20, g4, g9, g11, g13, g15, g21, h10, h12, h14, h16, j9, j11, j13, j15, k1, k3, k4, k10, k12, k14, k16, k21, k22, k24, l9, l11, l13, l15, m10, m12, m14, m16, n1, n4, n9, n11, n13, n15, n21, n24, p1, p10, p12, p14, p16, p24, r9, r11, r13, r15, t1, t4, t10, t12, t14, t16, t21, t24, u9, u11, u13, u15, v10, v12, v14, v16, w3, w4, w9, w11, w13, w15, w21, w22, y1, y10, y12, y14, y16, y24, ac4, ac23, ac24, ad1, ae1, ae2, ae3, ae4, ae5, ae6, ae7, af2, af4, af7 mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 62 intel corporation 6. thermal specifications in order to achieve proper cooling of the processor, a thermal solution (e.g., heat spreader, heat pipe, or other heat transfer system) must make firm contact to the exposed processor die. the processor die must be clean before the thermal solution is attached or the processor may be damaged. during all operating environments, the processor case temperature, t case , must be within the specified range of 0c to 100c. an a/d converter attached to the thermal diode can be used to measure the processor core temperature to ensure compliance with this specification. the designer is responsible for insuring that the thermal diode and a/d converter accurately track the processor temperature. the designer should verify this by correlating sensor output temperature with a thermocouple placed directly on the die surface. refer to section 6.2 for more details. table 6.1 mobile pentium ii processor (0.18 m) power specifications symbol parameter min typ 1 max unit notes tdp thermal design power @ 400 mhz @ 366 mhz @ 333 mhz @ 300pe mhz @ 266pe mhz @ 266pe mhz low voltage 9.80 13.10 11.80 11.10 9.80 7.90 w w w w w w at 100 c 2, 3 p sgnt stop grant and auto halt power 1.25 w at 50c 3 p qs quick start and sleep power 500 mw at 50c 3 p dslp deep sleep power 150 mw at 50c 3 t case case temperature 0 100 c notes: 1. tdp typ is a recommendation based on the power dissipation of the processor while executing publicly available software under normal operating conditions at nominal voltages. contact your intel field sales representative for further information. 2. tdp max is a specification of the total power dissipation of the processor while executing a worst-case instruction mix under normal operating conditions at nominal voltages. it includes the power dissipated by all of the components within the processor. specified by design/characterization. 3. not 100% tested or guaranteed. the power specifications are composed of the current of the processor on the various voltage planes. these currents are measured and specified at high temperature in table 3.10. these 50c power specifications are determined by characterization of the processor currents at higher temperatures. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 63 6.1 thermal diode the mobile pentium ii processor has an on-die diode that can be used to monitor the die temperature. a thermal sensor located on the system electronics may use the diode to monitor the die temperature of the processor for thermal management purposes. table 6.2 and table 6.3 provide the diode interface and specifications. table 6.2 thermal diode interface signal name ball/pin number signal description thermda t3 thermal diode anode thermdc u3 thermal diode cathode table 6.3. thermal diode specifications symbol parameter min typ max unit notes i fw forward bias current 5 500 a note 1 n diode ideality factor 1.0057 1.0080 1.0125 notes 2, 4, 5 n diode ideality factor 1.0000 1.0065 1.0173 notes 3, 4, 5 notes: 1. intel does not support or recommend operation of the thermal diode under reverse bias. intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. for the 400 mhz processor. characterized at 100c. 3. for the 366 mhz processor and below. characterized at 35c. 4. not 100% tested. specified by design/characterization. 5. the ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode i/v equation: 1 q nkt v e i i d o mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 64 intel corporation 6.2 case temperature to verify that the proper t case (case temperature) is maintained for the processor, it should be measured at the center of the die on the package top surface. to minimize any measurement errors, the following techniques are recommended: use 36 gauge or finer diameter k, t or j type thermocouples. intels laboratory testing was done using a thermocouple made by omega (part number: 5tc-ttk-36-36). attach the thermocouple bead or junction to the center of the die on the top package surface using highly thermally conductive cements. intels laboratory testing was done using omega bond (part number: ob100). thermal grease provides equivalent temperature measurement results when used correctly but is not as mechanically resilient as cement. the thermocouple should be attached at a 90 angle as shown in figure 6.1. a horizontal thermocouple mount is acceptable. v0028-00 figure 6.1 technique for measuring case temperature mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 65 7. processor initialization and configuration 7.1 description the mobile pentium ? ii processor has some configuration options that are determined by hardware and some that are determined by software. the processor samples its hardware configuration at reset, on the active-to-inactive transition of reset#. most of the configuration options for the mobile pentium ii processor are identical to those of the pentium ii processor. the pentium ? ii processor developers manual (order number 243502) describes these configuration options. new configuration options for the mobile pentium ii processor are described in the remainder of this section. 7.1.1 quick start enable the processor normally enters the stop grant state when the stpclk# signal is asserted, but it will enter the quick start state instead if a15# is sampled active on the reset# signals active-to- inactive transition. the quick start state supports snoops from the bus priority device like the stop grant state, but it does not support symmetric master snoops, nor is the latching of interrupts supported. a 1 in bit position 5 of the power-on configuration register indicates that the quick start state has been enabled. 7.1.2 system bus frequency the current generation mobile pentium ii processor will only function with a system bus frequency of 66 mhz, but future generations may operate at 100 mhz. bit position 19 of the power- on configuration register indicates at which speed a processor will run. a 0 in bit 19 indicates a 66-mhz bus frequency and a 1 indicates a 100-mhz bus frequency. 7.1.3 apic disable the apic has been removed as a feature of the mobile pentium ii processor. the picclk and picd[1:0] signals must be tied to v ss with a 1k resistor to disable the apic. driving picd0 low at reset has the effect of clearing the apic global enable bit in the apic base msr. this bit is normally set when the processor is reset, but when it is cleared the apic is completely disabled until the next reset. 7.2 clock frequencies and ratios the mobile pentium ii processor uses a clock design in which the bus clock is multiplied by a ratio to produce the processors internal (or core) clock. the bus fraction locking scheme implemented in the processor permanently sets the clock ratio multiplier to the corresponding processor marked frequency. section 3.3 describes how this is done. the bus ratio programmed into the processor is visible in bit positions 22 to 25 of the power-on configuration register. table 3.4 shows the 4-bit codes in the power-on configuration register and their corresponding bus ratios. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 66 intel corporation 8. processor interface 8.1 alphabetical signal reference except for bclk, the 1.5v tolerant signals are for the 400 mhz; the 2.5v tolerant signals are for the 366 mhz and below. a[35:3]# (i/o - low power gtl+) the a[35:3]# (address) signals define a 2 36 -byte physical memory address space. when ads# is active, these signals transmit the address of a transaction; when ads# is inactive, these signals transmit transaction information. these signals must be connected to the appropriate balls/pins of both agents on the system bus. the a[35:24]# signals are protected with the ap1# parity signal, and the a[23:3]# signals are protected with the ap0# parity signal. on the active-to-inactive transition of reset#, each processor bus agent samples a[35:3]# signals to determine its power-on configuration. see section 7 of this document and the pentium ? ii processor developers manual for details. a20m# (i - 1.5v/2.5v tolerant) if the a20m# (address-20 mask) input signal is asserted, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap-around at the 1-mbyte boundary. assertion of a20m# is only supported in real mode. ads# (i/o - low power gtl+) the ads# (address strobe) signal is asserted to indicate the validity of a transaction address on the a[35:3]# signals. both bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop or deferred reply id match operations associated with the new transaction. this signal must be connected to the appropriate balls/pins on both agents on the system bus. aerr# (i/o - low power gtl+) the aerr# (address parity error) signal is observed and driven by both system bus agents, and if used, must be connected to the appropriate balls of both agents on the system bus. aerr# observation is optionally enabled during power-on configuration; if enabled, a valid assertion of aerr# aborts the current transaction. if aerr# observation is disabled during power-on configuration, a central agent may handle an assertion of aerr# as appropriate to the error handling architecture of the system. the aerr# processor bus pin is removed as a processor feature for mobile pentium? ii processor at 400 mhz. the pin must still be terminated to vcc through a 120 pull-up resistor. but the processor must not be configured to drive or observe the pin. ap[1:0]# (i/o - low power gtl+) the ap[1:0]# (address parity) signals are driven by the request initiator along with ads#, a[35:3]#, req[4:0]# and rp#. ap1# covers a[35:24]#. ap0# covers a[23:3]#. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# should be connected to the appropriate balls/pins on both agents on the system bus. bclk (i - 2.5v tolerant) the bclk (bus clock) signal determines the system bus frequency. both system bus agents must receive this signal to drive their outputs and latch their inputs on the bclk rising edge. all external timing parameters are specified with respect to the bclk signal. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 67 berr# (i/o - low power gtl+) the berr# (bus error) signal is asserted to indicate an unrecoverable error without a bus protocol violation. it may be driven by either system bus agent, and must be connected to the appropriate balls/pins of both agents, if used. however, the mobile pentium? ii processor does not observe assertions of the berr# signal. berr# assertion conditions are defined by the system configuration. configuration options enable the berr# driver as follows: enabled or disabled asserted optionally for internal errors along with ierr# asserted optionally by the request initiator of a bus transaction after it observes an error asserted by any bus agent when it observes an error in a bus transaction binit# (i/o - low power gtl+) the binit# (bus initialization) signal may be observed and driven by both system bus agents, and must be connected to the appropriate balls/pins of both agents, if used. if the binit# driver is enabled during the power-on configuration, binit# is asserted to signal any bus condition that prevents reliable future information. if binit# is enabled during power-on configuration, and binit# is sampled asserted, all bus state machines are reset and any data which was in transit is lost. all agents reset their rotating id for bus arbitration to the state after reset, and internal count information is lost. the l1 and l2 caches are not affected. if binit# is disabled during power-on configuration, a central agent may handle an assertion of binit# as appropriate to the machine check architecture (mca) of the system. bnr# (i/o - low power gtl+) the bnr# (block next request) signal is used to assert a bus stall by any bus agent that is unable to accept new bus transactions. during a bus stall, the current bus owner cannot issue any new transactions. since multiple agents may need to request a bus stall simultaneously, bnr# is a wired-or signal which must be connected to the appropriate balls/pins of both agents on the system bus. in order to avoid wire-or glitches associated with simultaneous edge transitions driven by multiple drivers, bnr# is activated on specific clock edges and sampled on specific clock edges. bp[3:2]# (i/o - low power gtl+) the bp[3:2]# (breakpoint) signals are the system support group breakpoint signals. they are outputs from the processor that indicate the status of breakpoints. bpm[1:0]# (i/o - low power gtl+) the bpm[1:0]# (breakpoint monitor) signals are breakpoint and performance monitor signals. they are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpri# (i - low power gtl+) the bpri# (bus priority request) signal is used to arbitrate for ownership of the system bus. it must be connected to the appropriate balls/pins on both agents on the system bus. observing bpri# active (as asserted by the priority agent) causes the processor to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, and then releases the bus by deasserting bpri#. breq0# (i/o - low power gtl+) the breq0# (bus request) signal is a processor arbitration bus signal. the processor indicates that it wants ownership of the system bus by asserting the breq0# signal. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 68 intel corporation during power-up configuration, the central agent must assert the breq0# bus signal. the processor samples breq0# on the active-to-inactive transition of reset#. bsel (i - 1.5v/2.5v tolerant) the bsel (system bus speed select) signal is used to configure the processor for the system bus frequency. a 1 on this signal configures the processor for 100 mhz operation and a 0 configures it for 66 mhz operation. this signal must be connected to v ss . d[63:0]# (i/o - low power gtl+) the d[63:0]# (data) signals are the data signals. these signals provide a 64-bit data path between both system bus agents, and must be connected to the appropriate balls/pins on both agents. the data driver asserts drdy# to indicate a valid data transfer. dbsy# (i/o - low power gtl+) the dbsy# (data bus busy) signal is asserted by the agent responsible for driving data on the system bus to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must be connected to the appropriate balls/pins on both agents on the system bus. defer# (i - low power gtl+) the defer# (defer) signal is asserted by an agent to indicate that the transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addressed memory agent or i/o agent. this signal must be connected to the appropriate balls/pins on both agents on the system bus. dep[7:0]# (i/o - low power gtl+) the dep[7:0]# (data bus ecc protection) signals provide optional ecc protection for the data bus. they are driven by the agent responsible for driving d[63:0]#, and must be connected to the appropriate balls/pins on both agents on the system bus if they are used. during power-on configuration, dep[7:0]# signals can be enabled for ecc checking or disabled for no checking. drdy# (i/o - low power gtl+) the drdy# (data ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-cycle data transfer, drdy# can be deasserted to insert idle clo cks. this signal must be connected to the appropriate balls/pins on both agents on the system bus. edgctrln (analog) this signal is used to configure the edge rate of the low power gtl+ output buffers. connect the edgctrln (edge rate control n-fet) signal to v cc with a 51 , 1% resistor. ferr# (o - 1.5v/2.5v tolerant open-drain) the ferr# (floating-point error) signal is asserted when the processor detects an unmasked floating- point error. ferr# is similar to the error# signal on the intel387 coprocessor, and is included for compatibility with systems using dos-type floating- point error reporting. flush# (i - 1.5v/2.5v tolerant) when the flush# (flush) input signal is asserted, the processor writes back all internal cache lines in the modified state and invalidates all internal cache lines. at the completion of a flush operation, the processor issues a flush acknowledge transaction. the processor stops caching any new data while the flush# signal remains asserted. on the active-to-inactive transition of reset#, each processor bus agent samples flush# to determine its power-on configuration. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 69 hit# (i/o - low power gtl+), hitm# (i/o - low power gtl+) the hit# (snoop hit) and hitm# (hit modified) signals convey transaction snoop operation results, and must be connected to the appropriate balls/pins on both agents on the system bus. either bus agent can assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. ierr# (o - 1.5v/2.5v tolerant open-drain) the ierr# (internal error) signal is asserted by the processor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the system bus. this transaction may optionally be converted to an external error signal (e.g., nmi) by system logic. the processor will keep ierr# asserted until it is handled in software or with the assertion of reset#, binit or init#. ignne# (i - 1.5v/2.5v tolerant) the ignne# (ignore numeric error) signal is asserted to force the processor to ignore a numeric error and continue to execute non-control floating- point instructions. if ignne# is deasserted, the processor freezes on a non-control floating-point instruction if a previous instruction caused an error. ignne# has no effect when the ne bit in control register 0 (cr0) is set. during active reset#, the processor begins sampling the a20m#, ignne#, intr and nmi values to determine the ratio of core-clock frequency to bus-clock frequency (see table 3.4). on the active-to-inactive transition of reset#, the processor latches these signals and freezes the frequency ratio internally. system logic must then release these signals for normal operation. init# (i - 1.5v/2.5v tolerant) the init# (initialization) signal is asserted to reset integer registers inside the processor without affecting the internal (l1 or l2) caches or the floating-point registers. the processor begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous input. if init# is sampled active on reset#'s active-to- inactive transition, then the processor executes its built-in self test (bist). intr (i - 1.5v/2.5v tolerant) the intr (interrupt) signal indicates that an external interrupt has been generated. the interrupt is maskable using the if bit in the eflags register. if the if bit is set, the processor vectors to the interrupt handler after completing the current instruction execution. upon recognizing the interrupt request, the processor issues a single interrupt acknowledge (inta) bus transaction. intr must remain active until the inta bus transaction to guarantee its recognition. intr must be deasserted for a minimum of two clocks to guarantee its inactive recognition. lock# (i/o - low power gtl+) the lock# (lock) signal indicates to the system that a sequence of transactions must occur atomically. this signal must be connected to the appropriate balls/pins on both agents on the system bus. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction through the end of the last transaction. when the priority agent asserts bpri# to arbitrate for bus ownership, it waits until it observes lock# deasserted. this enables the processor to retain bus ownership throughout the bus locked operation and guarantee the atomicity of lock. nmi (i - 1.5v/2.5v tolerant) the nmi (non-maskable interrupt) indicates that an external interrupt has been generated. asserting nmi causes an interrupt with an internally supplied vector value of 2. an external interrupt-acknowledge transaction is not generated. if nmi is asserted during the execution of an nmi service routine, it mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 70 intel corporation remains pending and is recognized after the iret is executed by the nmi service routine. at most, one assertion of nmi is held pending. nmi is rising-edge sensitive. active and inactive pulse widths must be a minimum of two clocks. picclk (i - 1.5v/2.5v tolerant) the picclk (apic clock) signal is an input clock to the processor and system logic or i/o apic that is required for operation of the processor, system logic and i/o apic components on the apic bus. picd[1:0] (i/o - 1.5v/2.5v tolerant open-drain) the picd[1:0] (apic data) signals are used for bidirectional serial message passing on the apic bus. they must be connected to the appropriate balls/pins of all apic bus agents, including the processor and the system logic or i/o apic components. if the picd0 signal is sampled low on the active-to-inactive transition of the reset# signal, then the apic is hardware disabled. prdy# (o - low power gtl+) the prdy# (probe ready) signal is a processor output used by debug tools to determine processor debug readiness. preq# (i - 1.5v/2.5v tolerant) the preq# (probe request) signal is used by debug tools to request debug operation of the processor. pwrgood (i - 2.5v/2.5v tolerant) pwrgood (power good) is a 1.5v tolerant input for the 400 mhz, and 2.5v tolerant for the 366 mhz and below. the processor requires this signal to be a clean indication that clo cks and the power supplies (v cc , v ccp , etc.) are stable and within their specifications. clean implies that the signal will remain low, (capable of sinking leakage current) and without glitches, from the time that the power supplies are turned on, until they come within specification. the signal will then transition monotonically to a high (1.5v or 2.5v) state. figure 8.1 illustrates the relationship of pwrgood to other system signals. pwrgood can be driven inactive at any time, but clocks and power must again be stable before the rising edge of pwrgood. it must also meet the minimum pulse width specified in table 3.16 (section 3.5), and be followed by a 1 ms reset# pulse. bclk pwrgood reset# d0026-00 1 msec v ih,min v cc , v ccp , v ref figure 8.1 pwrgood relationship at power-on mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 71 the pwrgood signal, which must be supplied to the processor, is used to protect internal circuits against voltage sequencing issues. the pwrgood signal should be driven high throughout boundary scan operation. req[4:0]# (i/o - low power gtl+) the req[4:0]# (request command) signals must be connected to the appropriate balls/pins on both agents on the system bus. they are asserted by the current bus owner when it drives a[35:3]# to define the currently active transaction type. reset# (i - low power gtl+) asserting the reset# signal resets the processor to a known state and invalidates the l1 and l2 caches without writing back modified (m state) lines. for a power-on type reset, reset# must stay active for at least 1 msec after v cc and bclk have reached their proper dc and ac specifications and after pwrgood has been asserted. when observing active reset#, all bus agents will deassert their outputs within two clocks. a number of bus signals are sampled at the active- to-inactive transition of reset# for the power-on configuration. the configuration options are described in section 7 and in the pentium ? ii processor developers manual . unless its outputs are tri-stated during power-on configuration, after an active-to-inactive transition of reset#, the processor optionally executes its built- in self-test (bist) and begins program execution at reset-vector 000ffff0h or fffffff0h. reset# must be connected to the appropriate balls/pins on both agents on the system bus. rp# (i/o - low power gtl+) the rp# (request parity) signal is driven by the request initiator, and provides parity protection on ads# and req[4:0]#. rp# should be connected to the appropriate balls/pins on both agents on the system bus. a correct parity signal is high if an even number of covered signals are low, and low if an odd number of covered signals are low. this definition allows parity to be high when all covered signals are high. rs[2:0]# (i - low power gtl+) the rs[2:0]# (response status) signals are driven by the response agent (the agent responsible for completion of the current transaction), and must be connected to the appropriate balls/pins on both agents on the system bus. rsp# (i - low power gtl+) the rsp# (response parity) signal is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of rs[2:0]#. rsp# provides parity protection for rs[2:0]#. rsp# should be connected to the appropriate balls/pins on both agents on the system bus. a correct parity signal is high if an even number of covered signals are low, and low if an odd number of covered signals are low. during idle state of rs[2:0]# (rs[2:0]#=000), rsp# is also high since it is not driven by any agent guaranteeing correct parity. slp# (i - 1.5v/2.5v tolerant) the slp# (sleep) signal, when asserted in the stop grant state, causes the processor to enter the sleep state. during the sleep state, the processor stops providing internal clock signals to all units, leaving only the phase-locked loop (pll) still running. the processor will not recognize snoop and interrupts in the sleep state. the processor will only recognize changes in the slp#, stpclk# and reset# signals while in the sleep state. if slp# is deasserted, the processor exits sleep state and returns to the stop grant state in which it restarts its internal clock to the bus and apic processor units. mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 72 intel corporation smi# (i - 1.5v/2.5v tolerant) the smi# (system management interrupt) is asserted asynchronously by system logic. on accepting a system management interrupt, the processor saves the current state and enters system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. stpclk# (i - 1.5v/2.5v tolerant) the stpclk# (stop clock) signal, when asserted, causes the processor to enter a low-power stop grant state. the processor issues a stop grant acknowledge special transaction, and stops providing internal clock signals to all units except the bus and apic units. the processor continues to snoop bus transactions and service interrupts while in the stop grant state. when stpclk# is deasserted, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no effect on the bus clock. tck (i - 1.5v/2.5v tolerant) the tck (test clock) signal provides the clock input for the test bus (also known as the test access port). tdi (i - 1.5v/2.5v tolerant) the tdi (test data in) signal transfers serial test data to the processor. tdi provides the serial input needed for jtag support. tdo (o - 1.5v/2.5v tolerant open-drain) the tdo (test data out) signal transfers serial test data from the processor. tdo provides the serial output needed for jtag support. thermda, thermdc (analog) the thermda (thermal diode anode) and thermdc (thermal diode cathode) signals connect to the anode and cathode of the on-die thermal diode. tms (i - 1.5v/2.5v tolerant) the tms (test mode select) signal is a jtag support signal used by debug tools. trdy# (i - low power gtl+) the trdy# (target ready) signal is asserted by the target to indicate that the target is ready to receive write or implicit writeback data transfer. trdy# must be connected to the appropriate balls/pins on both agents on the system bus. trst# (i - 1.5v/2.5v tolerant) the trst# (test port reset) signal resets the test access port (tap) logic. the mobile pentium? ii processor does not self-reset during power-on; therefore, it is necessary to drive this signal low during power-on reset. vtol (o C 1.6v tolerant open-drain) the vtol (voltage tolerance) signal indicates whether the processor has 2.5v tolerant cmos signals or 1.5v tolerant cmos signals. this signal is a high impedance pin on the 2.5v tolerant mobile pentium? ii processor at 366 mhz and below, and is shorted to vss on the 1.5v tolerant mobile pentium? ii processor at 400 mhz. it is safe to connect this signal to 1.6v with a pull-up resistor.. 8.2 signal summaries table 8.1 through table 8.4 list the attributes of the processor input, output, and i/o signals. mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 73 table 8.1 input signals name active level clock signal group qualified a20m# low asynch cmos always bclk high system bus always bpri# low bclk system bus always bsel high asynch implementation always defer# low bclk system bus always flush# low asynch cmos always ignne# low asynch cmos always init# low asynch system bus always intr high asynch cmos apic disabled mode nmi high asynch cmos apic disabled mode picclk high apic always preq# low asynch implementation always pwrgood high asynch implementation always reset# low bclk system bus always rs[2:0]# low bclk system bus always rsp# low bclk system bus always slp# low asynch implementation stop grant state smi# low asynch cmos always stpclk# low asynch implementation always tck high jtag tdi tck jtag tms tck jtag trdy# low bclk system bus response phase trst# low asynch jtag mobile pentium ? ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz 74 intel corporation table 8.2 output signals name active level clock signal group ferr# low asynch open-drain ierr# low asynch open-drain prdy# low bclk implementation tdo high tck jtag vtol high asynch implementation table 8.3 input/output signals (single driver) name active level clock signal group qualified a[35:3]# low bclk system bus ads#, ads#+1 ads# low bclk system bus always ap[1:0]# low bclk system bus ads#, ads#+1 breq0# low bclk system bus always bp[3:2]# low bclk system bus always bpm[1:0]# low bclk system bus always d[63:0]# low bclk system bus drdy# dbsy# low bclk system bus always dep[7:0]# low bclk system bus drdy# drdy# low bclk system bus always lock# low bclk system bus always req[4:0]# low bclk system bus ads#, ads#+1 rp# low bclk system bus ads#, ads#+1 mobile pentium ii processor in micro-pga and bga packages at 400 mhz, 366 mhz, 333 mhz, 300pe mhz, and 266pe mhz intel corporation 75 table 8.4 input/output signals (multiple driver) name active level clock signal group qualified aerr# low bclk system bus ads#+3 berr# low bclk system bus always binit# low bclk system bus always bnr# low bclk system bus always hit# low bclk system bus always hitm# low bclk system bus always picd[1:0] high picclk apic always united states, intel corporation 2200 mission college blvd., p .o. box 58119, santa clara, ca 95052-8119 tel: +1 408 765-8080 japan, intel japan k.k. 5-6 tokodai, tsukuba-shi, ibaraki-ken 300-26 tel: + 81-29847-8522 france, intel corporation s.a.r.l. 1, quai de grenelle, 75015 paris tel: +33 1-45717171 united kingdom, intel corporation (u.k.) ltd. pipers way, swindon, wiltshire, england sn3 1rj tel: +44 1-793-641440 germany, intel gmbh dornacher strasse 1 85622 feldkirchen/ muenchen tel: +49 89/99143-0 hong kong, intel semiconductor ltd. 32/f two pacific place, 88 queensway, central tel: +852 2844-4555 canada, intel semiconductor of canada, ltd. 190 attwell drive, suite 500 rexdale, ontario m9w 6h8 tel: +416 675-2438 brazil, intel semicondutores do brasil centro empresarial na??es unidas - edifcio torre oeste av. das na??es unidas, 12.901 - 18o. andar - brooklin novo 04578.000 s?o paulo - s.p. C brasil tel: +55-11-5505-2296 |
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